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| FUJITSU SEMICONDUCTOR DATA SHEET DS07-13702-4E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90520 Series MB90522/523/F523/V520 s DESCRIPTION The MB90520 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high-speed real-time processing. The instruction set of the F2MC-16LX CPU core inherits AT architecture of the F2MC* family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90520 series has peripheral resources of 8/10-bit A/D converter, 8-bit D/A converter, UART (SCI), extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1, I/O timer (16-bit free-run timers 1 and 2, input captures 0 and 1 (ICU), output compares 0 and 1 (OCU)), and an LCD controller/driver. *:F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. s FEATURES * Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). The system can be operated by a sub-clock (rated at 32.768 kHz). Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, four times the oscillation clock, operation at VCC of 5.0 V) (Continued) s PACKAGES 120-pin Plastic LQFP 120-pin Plastic QFP (FPT-120P-M05) (FPT-120P-M13) MB90520 Series (Continued) * Maximum memory space 16 Mbytes * Instruction set optimized for controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by 32-bit accumulator * Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed 4-byte instruction queue * Enhanced interrupt function 8 levels, 34 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS): Up to 16 channels * Embedded ROM size and types Mask ROM: 64 kbytes/128 kbytes Flash ROM: 128 kbytes * Embedded RAM size Mask ROM: 4 kbytes Flash ROM: 4 kbytes Evaluation product: 6 kbytes * Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware stand-by mode Clock mode (mode in which other than sub-clock and timebase timer are stopped) * Process CMOS technology * I/O port General-purpose I/O ports (CMOS): 53 ports General-purpose I/O ports (via pull-up resistors): 24 ports General-purpose I/O ports (open-drain): 8 ports Total: 85 ports * Timer Timebase timer/watchdog timer: 1 channel 8/16-bit PPG timers 0, 1: 8-bit x 2 channels or 16-bit x 1 channel * 16-bit re-load timers 0, 1: 2 channels (Continued) 2 MB90520 Series (Continued) * 16-bit I/O timer 16-bit free-run timers 1, 2: 2 channels Input captures 0, 1 (ICU): Generates an interrupt request by latching a 16-bit free-run timer counter value upon detection of an edge input to the pin. Output compares 0, 1 (OCU): Generates an interrupt request and reverses the output level upon detection of a match between the 16-bit free-run timer counter value and the compare setting value. 8/16-bit up/down counter/timers 0, 1: 1 channel (8-bit x 2 channels) * Extended I/O serial interfaces 0, 1: 1 channel * UART (SCI) With full-duplex double buffer Clock asynchronized or clock synchronized transmission can be selectively used. * DTP/external interrupt circuit (8 channels) A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered by an external input. * Wake-up interrupt Receives external interrupt requests and generates an interrupt request upon an "L" level input. * Delayed interrupt generation module Generates an interrupt request for switching tasks. * 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. Conversion time: minimum 15.0 s (at machine clock frequency of 16 MHz, including sampling time) * 8-bit D/A converter (based on the R-2R system) 8-bit resolution: 2 channels (independent) Setup time: 12.5 s * Clock timer: 1 channel * LCD controller/driver A common driver and a segment driver that can directly drive the LCD (liquid crystal display) panel * Clock output function Note: Do not set external bus mode for the MB90520 series because it cannot be operated in this mode. 3 MB90520 Series s PRODUCT LINEUP Part number Item Classification ROM size RAM size MB90522 MB90523 MB90F523 MB90V520 Mask ROM product 64 kbytes 4 kbytes Flash ROM product Evaluation product 128 kbytes None 6 kbytes Number of instructions: 351 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits CPU functions Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz) Interrupt processing time: 1.5 s (at machine clock frequency of 16 MHz, minimum value) General-purpose I/O ports (CMOS output): 53 General-purpose I/O ports (via pull-up resistor): 24 General-purpose I/O ports (N-ch open-drain output): 8 Total: 85 Clock synchronized transmission (62.5 kbps to 1 Mbps) Clock asynchronized transmission (1202 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. Conversion precision: 8/10-bit can be selectively used. Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels: 1 (8-bit x 2 channels) PPG operation of 8-bit or 16-bit Pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 s (at machine clock frequency of 16 MHz) Number of channels: 1 (8-bit x 2 channels) Event input: 6 channels 8-bit up/down counter/timer used: 2 channels 8-bit re-load/compare function supported: 1 channel Number of channels: 2 Overflow interrupts Ports UART (SCI) 8/10-bit A/D converter 8/16-bit PPG timers 0, 1 8/16-bit up/down counter/ timers 0, 1 16-bit I/O timer 16-bit free-run timers 1, 2 (Continued) 4 MB90520 Series (Continued) Part number MB90523 Item Output compares 0, 1 (OCU) Input captures 0, 1 (ICU) DTP/external interrupt circuit Number of channels: 8 Pin input factor: Match signal of compare register Number of channels: 2 Rewriting register value upon pin input (rising, falling, or both edges) Number of inputs: 8 Started by rising edge, falling edge, "H" level input, or "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. Number of inputs: 8 Started by "L" level input. Interrupt generation module for switching tasks Used in real-time operating systems. Clock synchronized transmission (3125 bps to 1 Mbps) LSB first/MSB first 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) 8-bit resolution Number of channels: 2 channels Based on R-2R system Number of common output pins: 4 Number of segment output pins: 32 Number of power supply pins for LCD drive: 4 RAM for LCD indication: 16 bytes Booster for LCD drive: Internal Split resistor for LCD drive: Internal Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by CMOS 3.0 V to 5.5 V 4.0 V to 5.5 V 3.0 V to 5.5 V MB90523 MB90F523 MB90V520 16-bit I/O timer Wake-up intrrupt Delayed interrupt generation module Extended I/O serial interfaces 0, 1 Timebase timer 8-bit D/A converter LCD controller/driver Watchdog timer Low-power consumption (stand-by) mode Process Power supply voltage for operation* * : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") Assurance for the MB90V520 is given only for operation with a tool at a power voltage of 3.0 V to 5.5 V, an operating temperature of 0 to 55 degrees centigrade, and an operating frequency of 1 MHz to 16 MHz. 5 MB90520 Series s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-120P-M05 FPT-120P-M13 : Available x : Not available MB90522 MB90523 MB90F523 Note: For more information about each package, see section "s Package Dimensions." s DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation chip, note the difference between the evaluation chip and the chip actually used. The following items must be taken into consideration. * The MB90V520 does not have an internal ROM. However, operations equivalent to those performed by a chip with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by setting the development tool. * In the MB90V520, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.) * In the MB90522, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. * In the MB90523/F523, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to bank FE and bank FF. 6 MB90520 Series s PIN ASSIGNMENT (Top view) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 P31/CKOT P32/OUT0 P33/OUT1 P34/OUT2 P35/OUT3 P36/PG00 P37/PG01 VCC P40/PG10 P41/PG11 P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 PA0/SEG08 PA1/SEG09 PA2/SEG10 PA3/SEG11 PA4/SEG12 PA5/SEG13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P30 VSS P27/ADTG P26/ZIN0/INT7 P25/BIN0 P24/AIN0 P23/IC11 P22/IC10 P21/IC01 P20/IC00 P17/WI7 P16/WI6 P15/WI5 P14/WI4 P13/WI3 P12/WI2 P11/WI1 P10/WI0 P07 P06/INT6 P05/INT5 P04/INT4 P03/INT3 P02/INT2 P01/INT1 P00/INT0 VCC X1 X0 VSS RST MD0 MD1 MD2 HST V3 V2 V1 V0 P97/SEG31 P96/SEG30 P95/SEG29 P94/SEG28 P93/SEG27 P92/SEG26 P91/SEG25 X0A X1A P90/SEG24 P87/SEG23 P86/SEG22 P85/SEG21 P84/SEG20 P83/SEG19 P82/SEG18 P81/SEG17 P80/SEG16 VSS P77/COM3 P76/COM2 PA6/SEG14 PA7/SEG15 VSS C P50/SIN2/AIN1 P51/SOT2/BIN1 P52/SCK2/ZIN1 DVCC DVSS P53/DA0 P54/DA1 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 VCC P70/TI0/OUT4 P71/TO0/OUT5 P72/TI1/OUT6 P73/TO1/OUT7 P74/COM0 P75/COM1 (FPT-120P-M05) (FPT-120P-M13) 7 MB90520 Series s PIN DESCRIPTION Pin no. LQFP-120*1 QFP-120*2 92, 93 74, 73 89 to 87 90 86 95 to 101 Pin name X0, X1 X0A, X1A MD0 to MD2 RST HST P00 to P06 Circuit type A B C C C D Function This is a high-speed crystal oscillator pin. This is a low-speed crystal oscillator pin. This is an input pin for selecting operation modes. Connect directly to VCC or VSS. This is an external reset request signal input pin. This is a hardware stand-by input pin. This is a general-purpose I/O port. This function can be set by the port 0 input pull-up resistor setup register (RDR0) for input. For output, however, this function is invalid. This is a request input pin of the DTP/external interrupt circuit ch.0 to ch.6. D This is a general-purpose I/O port. This function can be set by the port 0 input pull-up resistor setup register (RDR0) for input. For output, however, this function is invalid. This is a general-purpose I/O port. This function can be set by the port 1 input pull-up resistor setup register (RDR1) for input. For output, however, this function is invalid. This is an I/O pin for wake-up interrupts. E This is a general-purpose I/O port. INT0 to INT6 102 P07 103 to 110 P10 to 17 D WI0 to WI7 111, 112, 113, 114 P20, P21, P22, P23 IC00, IC01, IC10, IC11 115 P24 AIN0 116 P25 BIN0 *1: FPT-120P-M05 *2: FPT-120P-M13 E E This is a trigger input pin for input capture (ICU) 0 and 1. Since this input is used as required for input capture 0 and 1 (ICU) ch.0, ch.01, ch.10 and ch.11 input operation, output by other functions must be suspended except for intentional operation. This is a general-purpose I/O port. This port can be used as count clock A input for 8/16-bit up/down counter/timer 0. This is a general-purpose I/O port. This port can be used as count clock B input for 8/16-bit up/down counter/timer 0. (Continued) 8 MB90520 Series Pin no. LQFP-120*1 QFP-120*2 117 Pin name P26 ZIN0 INT7 118 P27 ADTG Circuit type E Function This is a general-purpose I/O port. This port can be used as count clock Z input for 8/16-bit up/down counter/timer 0. This is a request input pin of the DTP/external interrupt circuit ch.7. E This is a general-purpose I/O port. This is an external trigger input pin of the 8/10-bit A/D converter. Since this input is used as required for 8/10-bit A/D converter input operation, output by other functions must be suspended except for intentional operation. 120 1 P30 P31 CKOT E E This is a general-purpose I/O port. This is a general-purpose I/O port. This is a clock monitor function output pin. This function is valid when clock monitor output is enabled. 2 P32 E This is a general-purpose I/O port. This function becomes valid when waveform output from the OUT0 is disabled. This is an event output pin for output compare 0 (OCU) ch.0. This function is valid when output for each channel is enabled. OUT0 3 P33 E This is a general-purpose I/O port. This function becomes valid when waveform output from the OUT1 is disabled. This is an event output pin for output compare 0 (OCU) ch.1. This function is valid when output for each channel is enabled. OUT1 4 P34 E This is a general-purpose I/O port. This function becomes valid when waveform output from the OUT2 is disabled. This is an event output pin for output compare 0 (OCU) ch.2. This function is valid when output for each channel is enabled. OUT2 5 P35 E This is a general-purpose I/O port. This function becomes valid when waveform output from the OUT3 is disabled. This is an event output pin for output compare 0 (OCU) ch.3. This function is valid when output for each channel is enabled. OUT3 6 P36 E This is a general-purpose I/O port. This function becomes valid when waveform output from the PG00 is disabled. This is an output pin of 8/16-bit PPG timer 0. This function becomes valid when waveform output from PG00 is enabled. PG00 *1: FPT-120P-M05 *2: FPT-120P-M13 (Continued) 9 MB90520 Series Pin no. LQFP-120*1 QFP-120*2 7 Pin name P37 Circuit type E Function This is a general-purpose I/O port. This function becomes valid when waveform output from the PG01 is disabled. This is an output pin of 8/16-bit PPG timer 0. This function becomes valid when waveform output from PG01 is enabled. PG01 9, 10 P40, P41 D This is a general-purpose I/O port. This function becomes valid when waveform output from the PG10 and PG11 are disabled. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is an output pin of 8/16-bit PPG timer 1. This function becomes valid when waveform outputs from PG10 and PG11 are enabled. PG10, PG11 11 P42 D This is a general-purpose I/O port. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial data input pin of UART (SCI). Because this input is used as required when UART (SCI) is performing input operations, it is necessary to stop outputs by other functions unless such outputs are made intentionally. When using other output functions as well, disable output during SIN operation. SIN0 12 P43 D This is a general-purpose I/O port. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial data output pin of UART (SCI). This function becomes valid when serial data output from UART (SCI) is enabled. SOT0 13 P44 D This is a general-purpose I/O port. This function can be set by the pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial clock I/O pin of UART (SCI). This function becomes valid when serial clock output from UART (SCI) is enabled. SCK0 14 P45 D This is a general-purpose I/O port. This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a data input pin for extended I/O serial interface 0. Since this input is used as required for serial data input operation, output by other functions must be suspended except for intentional operation. When using other output functions as well, disable output during SIN operation. SIN1 *1: FPT-120P-M05 *2: FPT-120P-M13 (Continued) 10 MB90520 Series Pin no. LQFP-120*1 QFP-120*2 15 Pin name P46 Circuit type D Function This is a general-purpose I/O port. This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a data output pin for extended I/O serial interface 0. This function becomes valid when serial data output from SOT1 is enabled. SOT1 16 P47 D This is a general-purpose I/O port. This function can be set by the port 4 input pull-up resistor setup register (RDR4) for input. For output, however, this function is invalid. This is a serial clock I/O pin for extended I/O serial interface 0. This function becomes valid when serial clock output from SCK1 is enabled. SCK1 35 P50 SIN2 D This is a general-purpose I/O port. This is a data input pin for extended I/O serial interface 1. Since this input is used as required for serial data input operation, output by other functions must be suspended except for intentional operation. This port can be used as count clock A input for 8/16-bit up/down counter/timer 1. AIN1 36 P51 SOT2 D This is a general-purpose I/O port. This is a data output pin for extended I/O serial interface 1. This function becomes valid when serial data output from SOT2 is enabled. This port can be used as count clock B input for 8/16-bit up/down counter/timer 1. BIN1 37 P52 SCK2 D This is a general-purpose I/O port. This is a serial clock I/O pin for extended I/O serial interface 1. This function becomes valid when serial clock output from serial SCK2 is enabled. This port can be used as control clock Z input for 8/16-bit up/down counter/timer 1. ZIN1 40, 41 P53, P54 DA0, DA1 46 to 53 P60 to P67 K I This is a general-purpose I/O port. These are analog signal output pins for 8-bit D/A converter ch.0 and ch.1. This is a general-purpose I/O port. The input function become valid when the analog input enable register (ADER) is set to select a port. These are analog input pins of the 8/10-bit A/D converter. This function is valid when the analog input enable register (ADER) is enabled. AN0 to AN7 *1: FPT-120P-M05 *2: FPT-120P-M13 (Continued) 11 MB90520 Series Pin no. LQFP-120*1 QFP-120*2 55, 57 Pin name P70, P72 TI0, TI1 Circuit type E Function This is a general-purpose I/O port. These are event input pins for 16-bit re-load timers 0 and 1. Since this input is used as required for 16-bit re-load timers 0 and 1 operation, output by other functions must be suspended except for intentional operation. These are event output pins for output compare 1 (OCU) ch.4 and ch.6. This function is valid when output for each channel is enabled. OUT4, OUT6 56, 58 P71, P73 TO0, TO1 OUT5, OUT7 59 to 62 P74 to P77 L E This is a general-purpose I/O port. This function is valid when TO0 and TO1 output are disabled. These are output pins for 16-bit re-load timers 0 and 1. This function is valid when TO0 and TO1 output are enabled. These are event output pins for output compare 1 (OCU) ch.5 and ch.7. This function is valid when output for each channel is enabled. This is a general-purpose I/O port. This function is valid with port output specified for the LCD controller/driver control register. These are common pins for the LCD controller/driver. This function is valid with common output specified for the LCD controller/driver control register. COM0 to COM3 64 to 71 P80 to P87 L This is a general-purpose I/O port. This function is valid with port output specified for the LCD controller/driver control register. These are segment outputs for the LCD controller/driver. This function is valid with segment output specified for the LCD controller/driver control register. SEG16 to SEG23 72, 75 to 81 P90, P91 to P97 M This is a general-purpose I/O port. The maximum IOL can be 10mA. This function is valid with port output specified for the LCD controller/driver control register. These are segment outputs for the LCD controller/driver. This function is valid with port output specified for the LCD controller/driver control register. SEG24, SEG25 to SEG31 17 to 24 25 to 32 SEG00 to SEG07 PA0 to PA7 F L These are pins dedicated to LCD segments 00 to 07 for the LCD controller/driver. This is a general-purpose I/O port. This function is valid with port output specified for the LCD controller/driver control register. These are pins for LCD segments 08 to 15 for the LCD controller/ driver. Units of four ports or segments can be selected by the internal register in the LCD controller. SEG08 to SEG15 *1: FPT-120P-M05 *2: FPT-120P-M13 12 (Continued) MB90520 Series (Continued) Pin no. LQFP-120*1 QFP-120*2 34 C Pin name Circuit type G Function This is a capacitance pin for power supply stabilization. Connect an external ceramic capacitor rated at about 0.1 F. This capacitor is not, however, required for the M90F523 (flash product). This is a pin for the reference power supply for the LCD controller/ driver. This is a power supply (5.0 V) input pin to the digital circuit. 82 to 85 8, 54, 94 33, 63, 91, 119 42 V0 to V3 VCC N Power supply Power supply VSS This provides the GND level (0.0 V) input pin for the digital circuit. AVCC H This is a power supply for the analog circuit. Make sure to turn on/turn off this power supply with a voltage exceeding AVCC applied to VCC. This is a reference voltage input to the analog circuit. Make sure to turn on/turn off this power supply with a voltage exceeding AVRH applied to AVCC. This is a reference voltage input to the analog circuit. This is a GND level of the analog circuit. This is the Vref input pin for the D/A converter. The voltage to be applied must not exceed VCC. This is the GND level pin for the D/A converter. The potential must be the same as VSS. 43 AVRH J 44 45 38 39 AVRL AVSS DVCC DVSS H H H H *1: FPT-120P-M05 *2: FPT-120P-M13 13 MB90520 Series s I/O CIRCUIT TYPE Type A X1 Nch Pch Pch Nch Circuit Remarks * High-speed oscillation feedback resistor approx. 1M X0 Standby control signal B X1A Nch Pch Pch Nch * Low-speed oscillation feedback resistor approx. 1M X0A Standby control signal C R Hysteresis input * Hysteresis input D Pch Pch Nch R Selecting signal with or without a input pull-up resistor * Hysteresis input (can be set with the input pull-up resistor) CMOS level output * Pull-up resistor approx. 50 k * Provided with a standby control function for input interruption Hysteresis input IOL = 4 mA Standby control for input interruption (Continued) 14 MB90520 Series Type E Pch Nch R Circuit VCC Remarks * CMOS hysteresis input/output * CMOS level output * Provided with a standby control function for input interruption Hysteresis input IOL = 4 mA Standby control for input interruption F Pch Nch R * Pins dedicated to segment output G Pch Nch * C pin output (Pin for capacitor connection) N.C. pin for the MB90F523 H Pch AVP Nch * Analog power input protector I VCC Pch Nch R Hysteresis input Standby control for input interruption * CMOS hysteresis input/output * Pin for analog output/CMOS output (During analog output, CMOS output is not produced.) (Analog output has priority over CMOS output: DAE = 1) * Provided with a standby control function for input interruption IOL = 4 mA DAO (Continued) 15 MB90520 Series Type J Pch Pch Nch Circuit Remarks * Input pin for ref+ power for the A/D converter Provided with power protection ANE AVR ANE Nch K Pch * Hysteresis input/analog input * CMOS output * Provided with a standby control for input interruption Nch R Hysteresis input Standby control for input interruption Analog input IOL = 4 mA L Pch * CMOS hysteresis input/output * Segment input * Standby control to cut off the input is available in segment input operation Nch R Hysteresis input Standby control for input interruption SEG IOL = 4 mA M Nch Nch R Hysteresis input * Hysteresis input * Nch open-drain output (High current for LCD drive) * Standby control to cut off the input is available in segment input operation IOL = 10 mA Standby control for input interruption N Pch R * Reference power supply pin for the LCD controller Nch IOL = 10 mA 16 MB90520 Series s HANDLING DEVICES 1. Ensuring that the Voltage does not exceed the Maximum Rating (to Avoid a Latch-up). In CMOS ICs, a latch-up phenomenon is caused when a voltage exceeding VCC or below VSS is applied to input or output pins or if a voltage exceeding the rating is applied across VCC and VSS. When a latch-up is caused, the power supply current may be dramatically increased, resulting in thermal breakdown of devices. To avoid the latch-up, make sure that the voltage does not exceed the maximum rating. In turning on/turning off the analog power supply, make sure the analog power voltages (AVCC, AVRH, DVCC) and analog input voltages do not exceed the digital voltage (VCC). And also make sure the voltages applied to the LCD power supply pins (V3 to V0) do not exceed the power supply voltage (VCC). 2. Handling Unused Pins * Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled-up or pull-down through at least 2 k resistance. * Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. 3. Notes on Using External Clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. * Using external clock X0 MB90520 series Open X1 4. Unused Sub Clock Mode If sub clock modes are not used, the oscillator should be connected to the X0A pin and X1A pin. 5. Power Supply Pins In products with multiple Vcc or Vss pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-ups. However, the pins should be connected to external powers and ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect Vcc and Vss pins via lowest impedance to power lines. It is recommended that a bypass capacitor of around 0.1 F be placed between the Vcc and Vss pins near the device. 17 MB90520 Series * Using power supply pins VCC VSS VCC VSS VCC VSS MB90520 series VCC VSS VSS VCC 6. Crystal Oscillator Circuit Noise around the X0 and X1 pins may cause abnormal operation in this device. In designing printed circuit boards, the X0 and X1 pins and crystal oscillator (or ceramic oscillator), as well as the bypass capacitor to the ground, should be placed as close as possible, and the related wiring should have as few crossings with other wiring as possible. Circuit board artwork in which the area of the X0 and X1 pins is surrounded by grounding is recommended for stabilizing the operation. 7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC, DVSS) and analog inputs (AN0 to AN7) after turning on the digital power supply (VCC). Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that AVRH and DVCC do not exceed AVCC (turning on/off the analog and digital supplies simultaneously is acceptable). 8. Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter and those of D/A converter to AVCC = DVCC = VCC, AVSS = AVRH = AVRL = VSS. 9. N.C. Pin The N.C. (internally connected) pin must be opened for use. 10.Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V). 11.Use of SEG/COM Pins for the LCD Controller/Driver as Ports In MB90520 series, pins SEG08 to SEG31, and COM0 to COM3 can also be used as general-purpose ports. The electrical standard is such that pins SEG08 to SEG23, and COM0 to COM3 have the same ratings as the CMOS output port, while pins SEG24 to SEG31 have the same ratings as the open-drain type. 18 MB90520 Series 12.Indeterminate outputs from ports 0 and 1 The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on. Pay attention to the port output timing shown as follow * Timming chart of indeterminate outputs from ports o and 1 Oscillation setting time2 Step-down circuit setting time 1 Vcc(power-supply pin) PONR(power-on reset) signal RST(external asynchronous reset) signal RST(internal reset) signal Oscillation clock signal KA(internal operation clock A) signal KB(internal operation clock B) signal PORT(port output)signal indereterminate period * : 1:Step-down circuit setting time : 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms) * : 2:Oscillation setting time: 218/oscillation clock frequency (oscillation cllock frequency of 16 MHz: 16.38 ms) 13.Initialization The device contains internal registers that can be initialized only by a power-on reset. To initialize the internal registers, restart the power supply. 14. Interrupt Recovery from Standby If an external interrupt is used for recovery from standby, use an "H" level input request. An "L" level request causes abnormal operation. 15.Precautions for Use of "DIV A, Ri", and "DIVW A, Ri" Instructions The signed multiplication-division instructions "DIV A, Ri", and "DIVW A, RWi" should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value "00h". If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than "00h," then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register. 16. Precautions for Use of REALOS Extended intelligent I/O service(EI2OS) cannot be used, when REALOS is used. 19 MB90520 Series s BLOCK DIAGRAM F2MC-16LX CPU X0, X1 X0A, X1A RST HST P07 P00/INT0 to P06/INT6 7 Oscillation clock Sub clock Clock control block*1 (including timebase timer) Port 0*2 7 DTP/ external interrupt circuit Port 8*5, 9*5, A*5 24 LCD controller/ driver 4 Port 7*4 16-bit re-load timer 0 16-bit re-load timer 1 16-bit I/O timer 2 Output 4 compare (OCU) 16-bit free-run timer 2 Input capture 1 (ICU) 8 8 8 8 4 4 P80/SEG16 to P87/SEG23 P90/SEG24 to P97/SEG31 PA0/SEG08 to PA7/SEG15 SEG00 to SEG07 V0 to V3 P74/COM0 to P77/COM3 P70/TI0/OUT4 P71/TO0/OUT5 P72/TI1/OUT6 P73/TO1/OUT7 Port 2*4 P24/AIN0 P25/BIN0 P26/ZIN0/INT7 3 8/16-bit up/down counter/timer 0, 1 16-bit I/O timer 1 2 Intrnal data bus P20/IC00 P21/IC01 2 Input capture 0 (ICU) 16-bit free-run timer 1 P22/IC10 P23/IC11 Port 2*4 Port 6*4 8 P32/OUT0 P33/OUT1 P34/OUT2 P35/OUT3 P31/CKOT P30 P36/PG00 P37/PG01 P40/PG10 P41/PG11 P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 4 compare 0 (OCU) Clock output Output 8 P60/AN0 to P67/AN7 AVCC AVSS AVRH AVRL P27/ADTG 8/10-bit A/D converter Port 3*4 2 2 8/16-bit PPG timer 0, 1 Port 2*4 Interrupt controller UART (SCI) Port 5*5 P50/SIN2/AIN1 P51/SOT2/BIN1 P52/SCK2/ZIN1 2 8-bit D/A converter x 2 ch. RAM ROM P53/DA0 P54/DA1 DVCC DVSS SIO ch.0 Port 4*2 Port 1*2 SIO ch.1 P10/WI0 to P17/WI7 8 8 Wake-up interrupt Other pins MD0 to MD2, C, VCC, VSS Notes: Actually 16-bit free-run timer 1 is supported although two free-run timers are seemingly supported. *1: The clock control circuit comprises a watchdog timer, a timebase timer, and a power consumption controller. *2: A register for setting a pull-up resistor is supported. *3: This is a high-current port for an LCD drive. *4: A register for setting a pull-up resistor is supported. Signals in the CMOS level are input and output. *5: Also used for LCD output. With this port used as is, Nch open-drain output develops. A register for setting a pull-up resistor is supported. 20 MB90520 Series s MEMORY MAP Single chip mode A mirroring function is supported. FFFFFFH ROM area Address #1 FE0000H 010000H ROM area (image of bank FF) Address #2 004000H 002000H Address #3 RAM Register 000100H 0000C0H 000000H Peripheral Part number MB90522 MB90523 MB90F523 Address #1* FF0000H FE0000H FE0000H Address #2 * 004000H 004000H 004000H Address #3 * 001100H 001100H 001100H : Internal access memory : Access prohibited *: Addresses #1, #2 and #3 vary with product type. Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the ROM without stating "far." For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are actually accessed. Since the ROM area of the FF bank exceeds 48k bytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH. 21 MB90520 Series s F2MC-16LX CPU PROGRAMMING MODEL * Dedicated registers AH AL : Accumlator (A) Dual 16-bit register used for storing results of calculation, etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) 16-bit pointer for containing a user stack address. : System stack pointer (SSP) 16-bit pointer for displaying the status of the system stack address. : Processor status (PS) 16-bit register for displaying the system status. : Program counter (PC) 16-bit register for displaying the storing location of the current instruction code. DPR : Direct page register (DPR) 8-bit register for specifying bit 8 through 15 of the operand address in the short direct addressing mode. : Program bank register (PCB) 8-bit register for displaying the program space. : Data bank register (DTB) 8-bit register for displaying the data space. : User stack bank register (USB) 8-bit register for displaying the user stack space. : System stack bank register (SSB) 8-bit register for displaying the system stack space. : Additional data bank register (ADB) 8-bit register for displaying the additional data space. USP SSP PS PC PCB DTB USB SSB ADB 8-bit 16-bit 32-bit 22 MB90520 Series * General-purpose registers Maximum of 32 banks R7 R5 R3 R1 RW3 R6 R4 R2 R0 RW7 RL3 RW6 RW5 RL2 RW4 RL1 RW2 RW1 RL0 000180H + (RP x 10H ) RW0 16-bit * Processor status (PS) ILM RP CCR bit 5 bit 4 S 1 T X bit 3 bit 2 N X Z X bit 1 V X bit 0 C X bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 PS Initial value -- : Unused X : Indeterminate ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 -- -- I 0 23 MB90520 Series s I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH EICR OCP5 OCU compare register ch.5 (Disabled) Wake-up interrupt enable register W Wake-up interrupt Abbreviated register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA LCDCMR OCP4 Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port 7/COM pin selection register OCU compare register ch.4 Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (Disabled) Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 7, LCD controller/driver Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXX B XXXX0 0 0 0 B XXXXXXXXB XXXXXXXXB 16-bit I/O timer (output compare 1 (OCU) section) EIFR DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ADER Wake-up interrupt flag register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Analog input enable register R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Wake-up interrupt XXXXXXX 0 B 00000000B 00000000B 00000000B 00000000B 00000000B XXX 0 0 0 0 0 B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B XXXXXXXXB XXXXXXXXB Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 6, A/Dconverter 16-bit I/O timer (output compare 1 (OCU) section) 00000000B (Continued) 24 MB90520 Series Abbreviated register name SMR SCR SIDR/ SODR SSR SMCSL0 SMCSH0 SDR0 CDCR SMCSL1 SMCSH1 SDR1 Read/ write R/W R/W or W R W R/W or R R/W R/W R/W R/W R/W R/W R/W (Disabled) OCS45 OCS67 ENIR EIRR ELVR OCU control status register ch.45 OCU control status register ch.67 DTP/interrupt enable register DTP/interrupt factor register Request level setting register R/W R/W R/W R/W R/W 16-bit I/O timer OCP6 ADCS1 ADCS2 ADCR1 ADCR2 DADR0 DADR1 DACR0 DACR1 CLKR OCU compare register ch.6 A/D control status register lower digits A/D control status register upper digits A/D data register lower digits A/D data register upper digits D/A converter data register ch.0 D/A converter data register ch.1 D/A control register 0 D/A control register 1 Clock output enable register R/W R/W R/W R R or W R/W R/W R/W R/W R/W Clock monitor function 8-bit D/A converter 8/10-bit A/D converter (output compare 1 (OCU) section) Address 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH Register name Serial mode register Serial control register Serial input data register/ serial output data register Serial status register Serial mode control lower status register 0 Serial mode control upper status register 0 Serial data register 0 Communications prescaler control register Serial mode control lower status register 1 Serial mode control upper status register 1 Serial data register 1 Resource name Initial value 00000000B 00000100B UART (SCI) XXXXXXXXB 00001X00B Extended I/O serial interface 0 Communications prescaler control register Extended I/O serial interface 1 XXXX0 0 0 0 B 00000010 B XXXXXXXXB 0 XXX 1 1 1 1 B XXXX0 0 0 0 B 00000010 B XXXXXXXXB 0 0 0 0XX0 0 B 16-bit I/O timer (output compare 1 (OCU) section) XXX 0 0 0 0 0 B 0 0 0 0XX0 0 B XXX 0 0 0 0 0 B 00000000B XXXXXXXX B 00000000B 00000000B XXXXXXXXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB 0 0 0 0 1 XXXB XXXXXXXXB XXXXXXXXB XXXXXXX 0 B XXXXXXX 0 B XXXX0 0 0 0 B DTP/external interrupt circuit (Continued) 25 MB90520 Series Abbreviated register name PRLL0 PRLH0 PRLL1 PRLH1 PPGC0 PPGC1 PPGOE0/ PPGOE1 Read/ Resource name write (Disabled) PPG0 re-load register L PPG0 re-load register H PPG1 re-load register L PPG1 re-load register H PPG0 operating mode control register PPG1 operating mode control register PPG0 and 1 output control registers (Disabled) TMCSR0 TMR0/ TMRLR0 TMCSR1 TMR1/ TMRLR1 IPCP0 IPCP1 ICS01 Timer control status register lower ch.0 Timer control status register upper ch.0 16-bit timer register upper, lower ch.0/ 16-bit re-load register upper, lower ch.0 Timer control status register lower ch.1 Timer control status register upper ch.1 16-bit timer register upper, lower ch.1/ 16-bit re-load register upper, lower ch.1 ICU data register ch.0 ICU data register ch.1 ICU control status register (Disabled) TCDT1 TCCS1 Free-run timer data register 1 Free-run timer control status register 1 Address 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H Register name Initial value R/W R/W R/W R/W R/W R/W R/W 8/16-bit PPG timer 0, 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0X0 0 0XX1 B 0X000001B 00000000B R/W 16-bit re-load timer 0 R/W R/W 16-bit re-load timer 1 R/W R 16-bit I/O timer R R/W (input compare 0, 1 (ICU) section) 00000000B XXXX 0 0 0 0 B XXXXXXXXB XXXXXXXXB 00000000B XXXX 0 0 0 0 B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit I/O timer (output compare 0 (OCU) section) R/W R/W 16-bit I/O timer (16-bit free-run timer 1 section) (Disabled) OCP0 OCP1 OCP2 OCP3 OCU compare register ch.0 OCU compare register ch.1 OCU compare register ch.2 OCU compare register ch.3 R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 26 MB90520 Series Abbreviated register name OCS01 OCS23 TCDT2 TCCS2 LCR0 LCR1 OCP7 Read/ write R/W R/W R/W R/W R/W R/W R/W (Disabled) ROMM ROM mirroring function selection register RAM for LCD indication Up/down count register 0 Up/down count register 1 Re-load compare register 0 Re-load compare register 1 Counter status register 0 W ROM mirroring function selection module LCD controller/ driver XXXXXXX 1 B Address 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H to 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH Register name OCU control status register ch.01 OCU control status register ch.23 Free-run timer data register 2 Free-run timer control status register 2 Resource name Initial value 0 0 0 0 XX 0 0 B 16-bit I/O timer (output compare 0 (OCU) section) XXX 0 0 0 0 0 B 0 0 0 0 XX 0 0 B XXX 0 0 0 0 0 B 00000000B 00000000B 00000000B 00010000B 00000000B XXXXXXXXB XXXXXXXXB 16-bit I/O timer (16-bit free-run timer 2 section) (Disabled) LCDC control registers 0 and 1 LCD controller/ driver 16-bit I/O timer (output compare 1 (OCU) section) OCU compare register ch.7 VRAM UDCR0 UDCR1 RCR0 RCR1 CSR0 CCRL0 CCRH0 CSR1 CCRL1 CCRH1 RDR0 RDR1 RDR4 R/W R R W W R/W (Reserved area)*3 XXXXXXXXB 00000000B 8/16-bit up/down counter/timer 0, 1 00000000B 00000000B 00000000B 00000000B X0000000B 00000000B 00000000B X0000000B X0000000B 00000000B 00000000B 00000000B Counter control register 0 Counter status register 1 R/W R/W (Reserved area)*3 8/16-bit up/down counter/timer 0, 1 Counter control register 1 Port 0 input pull-up resistor setup register Port 1 input pull-up resistor setup register Port 4 input pull-up resistor setup register R/W R/W R/W R/W 8/16-bit up/down counter/timer 0, 1 Port 0 Port 1 Port 4 (Continued) 27 MB90520 Series Abbreviated register name Read/ write Address 00008FH to 00009DH 00009EH Register name Resource name Initial value (Area used by the system)*3 Program address detection control status register Delayed interrupt factor generation/ cancellation register Low-power consumption mode control register Clock select register Address match detection function Delayed interrupt generation module Low-power consumption (stand-by) mode PACSR R/W 00000000B 00009FH 0000A0H 0000A1H 0000A2H to 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH to 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH DIRR LPMCR CKSCR R/W R/W or W R/W or R XXXXXXX 0 B 00011000B 11111100B (Disabled) WDTC TBTC WTC Watchdog timer control register Timebase timer control register Clock timer control register R or W R/W R/W or R (Disabled) FMCS ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Flash control register (Disabled) Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B (Continued) R/W Flash interface 1 XX 0 0 1 0 0 B Watchdog timer Timebase timer Clock timer XXXXXXXXB 1 XX 0 0 0 0 0 B 1X001000B 28 MB90520 Series (Continued) Address 0000BEH 0000BFH 0000C0H to 0000FFH 000100H to 00####H 00####H to 001FEFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 001FF6H to 001FFFH Descriptions for read/write R/W: Readable and writable R: Read only W: Write only Descriptions for initial value 0 : The initial value is "0." 1 : The initial value is "1." X : The initial value is indeterminate. *1: This area is the only external access area having an address of 0000FFH or lower. An access operation to this area is handled as that to external I/O area. *2: For details of the "RAM area", see the memory map. *3: The "reserved area" is basically disabled because it is used in the system. *4: "Area used by the system" is the area set by the resistor for evaluating tool. Notes: * For bits initialized by reset operations, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases in which initialization is performed or not performed, depending on the types of the reset. The value listed is the initial value in cases where initialization is per formed. * The addresses following 0000FFH are reserved. No external bus access signal is generated. * Boundary ####H between the "RAM area" and the" reserved area" varies with the product models. * Channels 0 to 3 of the OCU compare register use 16-bit free-run timer 2, while channels 4 to 7 of the OCU compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (ICU) 0 and 1. PADR1 PADR0 Abbreviated register name ICR14 ICR15 Register name Interrupt control register 14 Interrupt control register 15 Read/ write R/W R/W (External area)*1 Resource name Interrupt controller Initial value 00000111B 00000111B (RAM area)*2 (Reserved area)*3 Program address detection register 0 Program address detection register 1 Program address detection register 2 Program address detection register 3 Program address detection register 4 Program address detection register 5 R/W R/W R/W R/W R/W R/W Address match detection function XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Reserved area)*3 29 MB90520 Series s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS Interrupt source Reset INT9 instruction Exception 8/10-bit A/D converter Timebase timer DTP0/DTP1 (external interrupt 0/ external interrupt 1) 16-bit free-run timer 1 overflow Extended I/O serial interface 0 Wake-up interrupt Extended I/O serial interface 1 DTP2/DTP3 (external interrupt 2/ external interrupt 3) 8/16-bit PPG timer 0 counter borrow DTP4/DTP5 (external interrupt 4/ external interrupt 5) 8/16-bit up/down counter/timer 0 compare match 8/16-bit up/down counter/timer 0 overflow up/down inversion 8/16-bit PPG timer 1 counter borrow DTP6/DTP7 (external interrupt 6/ external interrupt 7) Output compare 1 (OCU) ch.4/ch.5 match Clock prescaler Output compare 1 (OCU) ch.6/ch.7 match 16-bit free-run timer 2 overflow 8/16-bit up/down counter/timer 1 compare match 8/16-bit up/down counter/timer 1 overflow, up/down inversion Input capture 0 (ICU) include Input capture 1 (ICU) include x x x x x x x EI2OS support x x x Interrupt vector Number # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H ICR03 FFFFB4H FFFFB0H ICR04 FFFFACH FFFFA0H ICR05 FFFFA4H FFFFA0H ICR06 FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H ICR09 FFFF84H FFFF80H ICR10 FFFF7CH 0000BAH Low 0000B9H ICR08 0000B8H 0000B6H 0000B5H 0000B4H 0000B3H ICR02 0000B2H ICR01 0000B1H Interrupt control register ICR -- -- -- ICR00 Address -- -- -- 0000B0H Priority High ICR07 0000B7H (Continued) 30 MB90520 Series (Continued) Interrupt source Output compare 0 (OCU) ch.0 match Output compare 0 (OCU) ch.1 match Output compare 0 (OCU) ch.2 match Output compare 0 (OCU) ch.3 match UART (SCI) reception complete 16-bit re-load timer 0 UART (SCI) transmission complete 16-bit re-load timer 1 Reserved Delayed interrupt generation module : Can be used x : Can not be used : Can be used with EI2OS stop function x x EI2OS support Interrupt vector Number # 33 # 34 # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 Address FFFF78H ICR11 FFFF74H FFFF70H ICR12 FFFF6CH FFFF68H ICR13 FFFF64H FFFF60H ICR14 FFFF5CH FFFF58H FFFF54H ICR15 0000BFH Low 0000BEH 0000BDH 0000BCH 0000BBH Interrupt control register ICR Address Priority High 31 MB90520 Series s PERIPHERALS 1. I/O Port (1) Input/Output Port Port 0 through A are general-purpose I/O ports having a combined function as a resource input. The I/O ports can be used as general-purpose I/O ports only in the single-chip mode. * Operation as output port The pin is configured as an output port by setting the corresponding bit of the DDR register to "1". Writing data to PDR register when the port is configured as output, the data is retained in the output latch in the PDR and directly output to the pin. The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR register. Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR register for output. However, values of bits configured as inputs by the DDR register are changed because input values to the pins are written into the output latch. To avoid this situation, configure the pins by the DDR register as output after writing output data to the PDR register when switching the bit used as input to output. * Operation as input port The pin is configured as input by setting the corresponding bit of the DDR register to "0." When the pin is configured as an input, the output buffer is turned off and the pin is put into a high-impedance status. When data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs are unaffected. Reading the PDR register reads out the pin level ("0" or "1"). 32 MB90520 Series (2) Register Configuration * Port 0 data register (PDR0) Address 000000H bit 7 P07 R/W bit 6 P06 R/W bit 14 P16 R/W bit 5 P05 R/W bit 13 P15 R/W bit 4 P04 R/W bit 12 P14 R/W bit 3 P03 R/W bit 11 P13 R/W bit 2 P02 R/W bit 10 P12 R/W bit 1 P01 R/W bit 9 P11 R/W bit 0 P00 R/W bit 8 P10 Initial value XXXXXXXX B Initial value XXXXXXXX B * Port 1 data register (PDR1) Address 000001H R/W bit 15 P17 R/W * Port 2 data register (PDR2) Address 000002H bit 7 P27 R/W bit 6 P26 R/W bit 5 P25 R/W bit 4 P24 R/W bit 3 P23 R/W bit 2 P22 R/W bit 1 P21 R/W bit 0 P20 R/W Initial value XXXXXXXX B * Port 3 data register (PDR3) Address 000003H bit 15 P37 R/W bit 14 P36 R/W bit 13 P35 R/W bit 12 P34 R/W bit 11 P33 R/W bit 10 P32 R/W bit 9 P31 R/W bit 8 P30 R/W Initial value XXXXXXXX B * Port 4 data register (PDR4) Address 000004H bit 7 P47 R/W bit 6 P46 R/W bit 14 -- -- bit 5 P45 R/W bit 13 -- -- bit 4 P44 R/W bit 12 P54 R/W bit 3 P43 R/W bit 11 P53 R/W bit 2 P42 R/W bit 10 P52 R/W bit 1 P41 R/W bit 9 P51 R/W bit 0 P40 R/W bit 8 P50 R/W Initial value XXXXXXXX B Initial value XXXXXXXX B * Port 5 data register (PDR5) Address 000005H bit 15 -- -- * Port 6 data register (PDR6) Address 000006H bit 7 P67 R/W bit 6 P66 R/W bit 5 P65 R/W bit 4 P64 R/W bit 3 P63 R/W bit 2 P62 R/W bit 1 P61 R/W bit 0 P60 R/W Initial value XXXXXXXX B * Port 7 data register (PDR7) Address 000007H bit 15 P77 R/W bit 14 P76 R/W bit 13 P75 R/W bit 12 P74 R/W bit 11 P73 R/W bit 10 P72 R/W bit 9 P71 R/W bit 8 P70 R/W Initial value XXXXXXXX B * Port 8 data register (PDR8) Address 000008H bit 7 P87 R/W bit 6 P86 R/W bit 14 P96 R/W bit 5 P85 R/W bit 13 P95 R/W bit 4 P84 R/W bit 12 P94 R/W bit 3 P83 R/W bit 11 P93 R/W bit 2 P82 R/W bit 10 P92 R/W bit 1 P81 R/W bit 9 P91 R/W bit 0 P80 R/W bit 8 P90 R/W Initial value XXXXXXXX B Initial value XXXXXXXX B * Port 9 data register (PDR9) Address 000009H bit 15 P97 R/W (Continued) 33 MB90520 Series * Port A data register (PDRA) Address 00000AH bit 7 PA7 R/W bit 6 PA6 R/W bit 6 D06 R/W bit 5 PA5 R/W bit 5 D05 R/W bit 4 PA4 R/W bit 4 D04 R/W bit 3 PA3 R/W bit 3 D03 R/W bit 2 PA2 R/W bit 2 D02 R/W bit 1 PA1 R/W bit 1 D01 R/W bit 0 PA0 R/W bit 0 D00 R/W Initial value 00000000 B Initial value XXXXXXXX B * Port 0 direction register (DDR0) Address 000010H bit 7 D07 R/W Initial value 00000000 B * Port 1 direction register (DDR1) Address 000011H bit 15 D17 R/W bit 14 D16 R/W bit 13 D15 R/W bit 12 D14 R/W bit 11 D13 R/W bit 10 D12 R/W bit 9 D11 R/W bit 8 D10 R/W * Port 2 direction register (DDR2) Address 000012H bit 7 D27 R/W bit 6 D26 R/W bit 14 D36 bit 5 D25 R/W bit 13 D35 bit 4 D24 R/W bit 12 D34 R/W bit 3 D23 R/W bit 11 D33 R/W bit 2 D22 R/W bit 10 D32 R/W bit 1 D21 R/W bit 9 D31 R/W bit 0 D20 R/W bit 8 D30 R/W Initial value 00000000 B Initial value 00000000 B * Port 3 direction register (DDR3) Address 000013H bit 15 D37 * Port 4 direction register (DDR4) Address 000014H bit 7 D47 R/W bit 6 D46 R/W bit 14 -- R/W bit 5 D45 R/W bit 13 -- R/W bit 4 D44 R/W bit 12 D54 R/W bit 3 D43 R/W bit 11 D53 R/W bit 2 D42 R/W bit 10 D52 R/W bit 1 D41 R/W bit 9 D51 R/W bit 0 D40 R/W bit 8 D50 R/W Initial value XXX0 0 0 0 0 B Initial value 00000000 B * Port 5 direction register (DDR5) Address 000015H bit 15 -- R/W * Port 6 direction register (DDR6) Address 000016H bit 7 D67 R/W bit 6 D66 R/W bit 14 D76 R/W bit 5 D65 R/W bit 13 D75 R/W bit 4 D64 R/W bit 12 D74 R/W bit 3 D63 R/W bit 11 D73 R/W bit 2 D62 R/W bit 10 D72 R/W bit 1 D61 R/W bit 9 D71 R/W bit 0 D60 R/W bit 8 D70 R/W Initial value 00000000 B Initial value 00000000 B * Port 7 direction register (DDR7) Address 000017H bit 15 D77 R/W * Port 8 direction register (DDR8) Address 000018H bit 7 D87 R/W bit 6 D86 R/W bit 5 D85 R/W bit 4 D84 R/W bit 3 D83 R/W bit 2 D82 R/W bit 1 D81 R/W bit 0 D80 R/W Initial value 00000000 B (Continued) 34 MB90520 Series (Continued) * Port 9 direction register (DDR9) Address 000019H bit 15 D97 R/W bit 14 D96 R/W bit 13 D95 R/W bit 12 D94 R/W bit 11 D93 R/W bit 10 D92 R/W bit 9 D91 R/W bit 8 D90 R/W Initial value 00000000 B * Port A direction register (DDRA) Address 00001AH bit 7 DA7 R/W bit 6 DA6 R/W bit 5 DA5 R/W bit 4 DA4 R/W bit 3 DA3 R/W bit 2 DA2 R/W bit 1 DA1 R/W bit 0 DA0 R/W Initial value 00000000 B * Port 0 input pull-up resistor setup register (RDR0) Address 00008CH bit 7 RD07 R/W Address 00008DH bit 15 RD17 R/W bit 6 RD06 R/W bit 14 RD16 R/W bit 5 RD05 R/W bit 13 RD15 R/W bit 4 RD04 R/W bit 12 RD14 R/W bit 3 RD03 R/W bit 11 RD13 R/W bit 2 RD02 R/W bit 10 RD12 R/W bit 1 RD01 R/W bit 9 RD11 R/W bit 0 RD00 R/W bit 8 RD10 R/W Initial value 00000000 B Initial value 00000000 B * Port 1 input pull-up resistor setup register (RDR1) * Port 4 input pull-up resistor setup register (RDR4) Address 00008EH bit 7 RD47 R/W Address 00001BH bit 15 ADE7 R/W bit 6 RD46 R/W bit 14 ADE6 R/W bit 5 RD45 R/W bit 13 ADE5 R/W bit 4 RD44 R/W bit 12 bit 3 RD43 R/W bit 11 bit 2 RD42 R/W bit 10 ADE2 R/W bit 1 RD41 R/W bit 9 ADE1 R/W bit 0 RD40 R/W bit 8 ADE0 R/W Initial value 11111111 B Initial value 00000000 B * Analog input enable register (ADER) ADE4 ADE3 R/W R/W * Port 7/COM pin selection register (LCDCMR) Address 00000BH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 bit 10 bit 9 bit 8 Initial value XXXX0 0 0 0 B COM3 COM2 COM1 COM0 R/W R/W R/W R/W R/W : Readable and writable X : Indeterminate -- : Undefined bits (read value undefined) 35 MB90520 Series (3) Block Diagram * Input/output port PDR (port data register) PDR read Internal data bus Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) DDR read Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode Nch Pin Pch * Input pull-up resistor setup register (RDR) PDR (port data register) To resource input PDR read Output latch PDR write DDR (port direction register) Internal data bus Direction latch DDR write Standby control (SPL=1) Nch Pch Pull-up resistor About 50 k (5.0 V) Pch Pin DDR read RDR latch RDR write RDR read RDR (input pull-up resistor setup register) Standby control: Stop, timebase timer mode and SPL=1 36 MB90520 Series * Analog input enable register (ADER) ADER (analog input enable register) ADER read ADER latch ADER write PDR (port data register) Internal data bus RMW (read-modify-write type instruction) To analog input PDR read Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) Pch Pin Nch DDR read Standby control: Stop, timebase timer mode and SPL=1 37 MB90520 Series 2. Timebase Timer The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types : 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK. The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer, etc. (1) Register Configuration * Timebase timer control register (TBTC) bit 15 Reserved R/W bit 14 -- -- bit 13 -- -- bit 12 TBIE R/W bit 11 bit 10 bit 9 bit 8 Initial value 1XX0 0 0 0 0 B Address 0000A9H TBOF TBR R/W R/W TBC1 TBC0 R/W R/W R/W: Readable and writable -- : Undefined bits (read value undefined) (2) Block Diagram To 8/16-bit PPG timer Timebase timer counter Divided-by-2 of HCLK x 21 x 2 2 x 2 3 To watchdog timer ... ... x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF To oscillation stabilization time selector of clock control block Power-on reset Start stop-mode CKSCR : MCS = 10*1 Counter clear circuit Interval timer selector Set TBOF Clear TBOF Timebase timer control register (TBTC) Timebase timer interrupt signal #12*2 Reserved -- -- TBIE TBOF TBR TBC1 TBC0 *1: Switch machine clock from oscillation clock to PLL clock *2: Interrupt number OF : Overflow HCLK : Oscillation clock frequency 38 MB90520 Series 3. Watchdog Timer The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when the counter is not cleared for a preset period of time. (1) Register Configuration * Watchdog timer control register (WDTC) Address 0000A8H bit 7 bit 6 bit 5 bit 4 bit 3 SRST R bit 2 WTE W bit 1 WT1 W bit 0 WT0 W PONR STBR WRST ERST R R R R Initial value XXXXXXXX B R : Read only W: Write only X : Indeterminate (2) Block Diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0 2 Watchdog timer CLR and start Overflow Start sleep-mode Start hold status Start stop-mode Counter clear control circuit Count clock selector CLR 2-bit counter CLR Watchdog timer reset generation circuit To internal reset generation circuit Clear (Timebase timer counter) Divided-by-2 of HCLK x 21 x 22 ... 4 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 HCLK : Oscillation clock frequency 39 MB90520 Series 4. 8/16-bit PPG Timer 0, 1 The 8/16-bit PPG timer is a 2-CH re-load timer module for outputting pulse having given frequencies/duty ratios. The two modules perform the following operation by combining functions. * 8-bit PPG timer output 2-CH independent output mode This is a mode for operating independent 2-CH 8-bit PPG timers, in which PG00 and PG10 pins correspond to outputs from PPG0 and PPG1 respectively. * 16-bit PPG timer output operation mode In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer 0 and 1 operating as a 16-bit timer. Because outputs during 16-bit PPG timer output operation mode are reversed by an underflow from PPG1, the same output pulses are output from PG10 and PG11 pins. * 8 + 8-bit PPG timer output operation mode In this mode, PPG0 is operated as an 8-bit prescaler register, in which an underflow output of PPG0 is used as a clock source for PPG1. A prescaler output of PPG0 is output from PG00 and PG01 pins. PPG output of PPG1 is output from PG10 and PG11 pins. * PPG output operation A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an external add-on circuit. 40 MB90520 Series (1) Register Configuration * PPG0 operating mode control register (PPGC0) Address 000044H bit 7 PEN0 R/W bit 6 -- -- bit 5 PE00 R/W bit 4 PIE0 R/W bit 3 PUF0 R/W bit 2 -- -- bit 1 -- -- bit 0 Reserved -- Initial value 0X0 0 0XX1 B * PPG1 operating mode control register (PPGC1) Address 000045H bit 15 PEN1 R/W bit 14 -- -- bit 13 PE10 R/W bit 12 PIE1 R/W bit 11 PUF1 R/W bit 10 MD1 R/W bit 9 bit 8 Initial value 0X0 0 0 0 0 1 B MD0 Reserved R/W R/W * PPG0 output control register (PPGOE0) Address 000046H bit 7 R/W Address 000046H bit 7 bit 6 R/W bit 6 bit 5 R/W bit 5 bit 4 R/W bit 4 bit 3 R/W bit 3 bit 2 R/W bit 2 bit 1 PE11 R/W bit 1 PE11 R/W bit 0 PE01 R/W bit 0 PE01 R/W Initial value 00000000 B Initial value 00000000 B PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 * PPG1 output control register (PPGOE1) PCS2 PCS1 R/W R/W PCS0 PCM2 PCM1 PCM0 R/W R/W R/W R/W * PPG0 re-load register H (PRLH0) Address 000041H R/W R/W R/W R/W R/W R/W R/W R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value XXXXXXXX B * PPG1 re-load register H (PRLH1) Address 000043H R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXX B R/W Address 000042H R/W R/W R/W R/W R/W R/W R/W R/W bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value XXXXXXXX B * PPG0 re-load register L (PRLL0) Address 000040H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * PPG1 re-load register L (PRLL1) R/W:Readable and writable X : Indeterminate -- : Undefined bits (read value undefined) 41 MB90520 Series (2) Block Diagram * Block diagram of 8/16-bit PPG timer 0 Data bus for "H" digits Data bus for "L" digits PPG0 re-load register PRLH0 PRLL0 PEN0 -- PPG0 operating mode control register (PPGC0) PE00 PIE0 PUF0 -- -- Reserved Temporary buffer (PRLBH0) R S 2 Q Interrupt request #19* Oprating mode control signal PPG1 underflow PPG0 underflow (to PPG1) Pulse selector Re-load selector L/H selector Count value Re-load Select signal Clear Underflow Down counter (PCNT0) CLK Reverse PPG0 output latch PPG output control circuit Count clock selector Pin P36/PG00 Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/) Pin P37/PG01 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01 PPG0, 1 output control register (PPGOE0,1) * : Interrupt number HCLK : Oscillation clock frequency : Machine clock frequency 42 MB90520 Series * Block diagram of 8/16-bit PPG timer 1 Data bus for "H" digits Data bus for "L" digits PPG1 re-load register PRLH0 Operating mode control signal Temporary buffer (PRLBH1) PRLL0 PEN1 -- 2 PPG1 operating mode control register (PPGC1) PEI0 PIE1 PUF1 MD1 MD0 Reserved R S Q Interrupt request #23* Re-load selector (L/H selector) Count value Re-load Select signal Clear Underflow Reverse PPG1 output latch Down counter (PCNT1) PPG1 underflow (to PPG0) CLK Pin P40/PG10 PPG output control circuit MD0 Pin PPG0 underflow Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/) P41/PG11 Count clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01 PPG0, 1 Output control register (PPGOE0, 1) * : Interrupt number HCLK : Oscillation clock frequency : Machine clock frequency 43 MB90520 Series 5. 16-bit Re-load Timer 0, 1 (With an Event Count Function) The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down by detecting a given edge of the pulse input to the external bus pin. Either of the two functions can be selectively used. For this timer, an "underflow" is defined as the timing of transition from the counter value of "0000H" to "FFFFH." According to this definition, an underflow occurs after a counter value of [re-load register setting value + 1] . In operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used. Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent I/O service (EI2OS). The MB90520 series has 2 channels of 16-bit re-load timers. (1) Register Configuration * Timer control status register upper digits ch.0, ch.1 (TMCSR0, TMCSR1 : H) Address TMCSR0 : 000049H TMCSR1 : 00004DH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 CSL1 R/W bit 10 bit 9 bit 8 Initial value XXXX0 0 0 0 B CSL0 MOD2 MOD1 R/W R/W R/W * Timer control status register lower digits ch.0, ch.1 (TMCSR0, TMCSR1 : L) Address TMCSR0 : 000048H TMCSR1 : 00004CH bit 7 bit 6 bit 5 bit 4 RELD R/W bit 3 INTE R/W bit 2 UF R/W bit 1 CNTE R/W bit 0 TRG R/W Initial value 00000000 B MOD0 OUTE OUTL R/W R/W R/W * 16-bit timer register upper and lower digits ch.0, ch.1 (TMR0, TMR1) Address TMR0 : 00004BH 00004AH TMR1 : 00004EH 00004FH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R R R R R R R R R R R R R R R R Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B * 16-bit re-load register upper and lower digits ch.0, ch.1 (TMRLR0, TMRLR1) Address TMRLR0 : 00004BH 00004AH TMRLR1 : 00004EH 00004FH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W W W W W W W W W W W W W W W W Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B R/W : Readable and writable R : Read only W : Write only X : Indeterminate -- : Undefined bits (read value undefined) 44 MB90520 Series (2) Block Diagram Internal data bus TMRLR0*1 Prescaler 3 Valid clock decision circuit Wait signal Clear Internal clock Pin Input control circuit External clock P70/TI0/OUT4*1 3 CLK Output control circuit Clock selecter Output signal generation circuit To UART*1 Pin EN P71/TO0/OUT5*1 Reverse Select signal Operation control circuit -- -- -- -- CSL1 CSL0 MOD2MOD1MOD0 OUTE OUTL RELD INTE UF CNTE TRG Clear EI2CS Interrupt request signal #38*1, *2 <#40> Timer control status register (TMCSR0)*1 45 MB90520 Series 6. 16-bit I/O Timer The 16-bit I/O timer module consists of two 16-bit free-run timers, two input capture circuits (ICU), and eight output comparators (OCU). This module allows two independent waveforms to be output on the basis of the 16-bit free-run timer. Input pulse width and external clock periods can, therefore, be measured. * Block diagram Internal data bus Input capture 0, 1 (ICU) 16-bit Dedicated Dedicated Output compare 0, 1 free-run timer 1, 2 (OCU) bus bus 46 MB90520 Series (1) 16-bit Free-run Timer 1, 2 The 16-bit free-run timer consists of a 16-bit up counter, a control register and a communications prescaler register. The value output from the timer counter is used as basic time (base timer) for input capture (ICU) and output compare (OCU). * A counter operation clock can be selected from four internal clocks (/4, /16, /64 and /256). * An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0 and 4. (Compare match requires mode settings.) * The counter value can be initialized to "0000H" by a reset, software clear or compare match with OCU compare register 0 and 4. * Register configuration * Free-run timer data register 1, 2 (TCDT1, TCDT2) Address TCDT1 : 000057H 000056H TCDT2 : 000067H 000066H bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 Initial value 00000000 B 00000000 B 00000000 B 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * Free-run timer control status register 1, 2 (TCCS1, TCCS2) Address TCCS1 : 000058H TCCS2 : 000068H bit 7 Reserved R/W R/W: Readable and writable bit 6 IVF R/W bit 5 IVFE R/W bit 4 bit 3 bit 2 CLR R/W bit 1 CLK1 R/W bit 0 CLK0 R/W Initial value 00000000 B 00000000 B STOP MODE R/W R/W * Block diagram Count value output to ICO and OCU Free-run timer data register (TCDT1)*1 Communications prescaler register 2 Free-run timer control status register (TCCS1) *1 OCU compare register 0 match signal 16-bit free-run timer interrupt request #14*1, *2 <#28> *1: The timer has ch.1 and ch.2, and figures bracketed by < > are for ch.2. *2: Interrupt number : Machine clock frequency OF : Overflow Internal data bus 47 MB90520 Series (2) Input Capture 0, 1 (ICU) The input capture (ICU) generates an interrupt request to the CPU while storing the current counter value of the 16-bit free-run timer to the ICU data register (IPCP) upon input of a trigger edge from the external pin. There are two sets (two channels) of input capture external pins and ICU data registers, enabling measurements of a maximum of four events. * The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling measurements of a maximum of four events. * Trigger edge direction can be selected from rising/falling/both edges. * The input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16-bit free-run timer to the ICU data register (IPCP). * The input compare conforms to the extended intelligent I/O service (EI2OS). * The input capture ( ICU) function is suited for measurements of intervals (frequencies) and pulse-widths. * Register configuration * ICU data register ch.0 ch.1 (IPCP0, IPCP1) Address IPCP0(upper) : 000051H IPCP1(upper) : 000053H bit 15 CP15 R bit 7 CP07 R bit 14 CP14 R bit 6 CP06 R bit 13 CP13 R bit 5 CP05 R bit 12 CP12 R bit 4 CP04 R bit 11 CP11 R bit 3 CP03 R bit 10 CP10 R bit 2 CP02 R bit 9 CP09 R bit 1 CP01 R bit 8 CP08 R bit 0 CP00 R Initial value XXXXXXXXB Address IPCP0(lower) : 000050H IPCP1(lower) : 000052H Initial value XXXXXXXXB Note: This register holds a 16-bit free-run timer value when the valid edge of the corresponding external pin input waveform is detected. (This register can be word-accessed, but not programmed.) * ICU control status register (ICS01) Address 000054H bit 7 ICP1 R/W bit 6 ICP0 R/W bit 5 ICE1 R/W bit 4 ICE0 R/W bit 3 EG11 R/W bit 2 EG10 R/W bit 1 EG01 R/W bit 0 EG00 R/W Initial value 00000000B R/W : Readable and writable R : Read only X : Indeterminate 48 MB90520 Series * Block diagram Internal data bus Latch signal P20/IC00 Pin P21/IC01 Pin P22/IC10 Pin P23/IC11 Pin 2 Data latch signal IPCP0(upper) 2 IPCP1(upper) IPCP1(lower) 16 IPCP0(lower) 16 16-bit free-run timer 1, 2 Edge detection circuit Output latch ICU data register (IPCP) ICU control status register (ICS01) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Interrupt request #31* Interrupt request #32* * : Interrupt number 49 MB90520 Series (3) Output Compare 0, 1 (OCU) The output compare (OCU) is two sets of compare units each consisting of an eight-channel OCU compare register, a comparator and a control register. An interrupt request can be generated for each channel upon a match detection by performing time-division comparison between the OCU compare data register setting value and the counter value of the 16-bit free-run timer. The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the CMOD bit. * Register Configuration * OCU control status register ch.01, ch.23, ch.45, ch.67 (OCS01, OCS23, OCS45, OCS67) Address ch.01 : OCS01 (upper) : 0000063H ch.23 : OCS23 (upper) : 0000065H ch.45 : OCS45 (upper) : 000002DH ch.67 : OCS67 (upper) : 000002FH Address ch.01 : OCS01 (lower) : 000062H ch.23 : OCS23 (lower) : 000064H ch.45 : OCS45 (lower) : 00002CH ch.67 : OCS67 (lower) : 00002EH bit 15 -- -- bit 7 ICP1 R/W bit 14 -- -- bit 6 ICP0 R/W bit 13 -- -- bit 5 ICE1 R/W bit 12 bit 11 bit 10 bit 9 bit 8 OTD0 R/W bit 0 Initial value ICE0 R/W -- -- -- -- CST1 R/W CST0 0 0 0 0XX0 0 B R/W Initial value XXX0 0 0 0 0 B CMOD OTE1 R/W bit 4 R/W bit 3 OTE0 OTD1 R/W bit 2 R/W bit 1 * OCU control status register ch.0 to ch.7 (OCS0 to OCS7) Address ch.0 : OCP0 (upper) : 00005BH ch.1 : OCP1 (upper) : 00005DH ch.2 : OCP2 (upper) : 00005FH ch.3 : OCP3 (upper) : 000061H ch.4 : OCP4 (upper) : 00000DH ch.5 : OCP5 (upper) : 00001DH ch.6 : OCP6 (upper) : 000035H ch.7 : OCP7 (upper) : 00006DH bit 15 C15 R/W bit 14 C14 R/W bit 13 C13 R/W bit 12 C12 R/W bit 11 C11 R/W bit 10 C10 R/W bit 9 C09 R/W bit 8 C08 R/W Initial value XXXXXXXX B Address ch.0 : OCP0 (lower) : 00005AH ch.1 : OCP1 (lower) : 00005CH ch.2 : OCP2 (lower) : 00005EH ch.3 : OCP3 (lower) : 000060H ch.4 : OCP4 (lower) : 00000CH ch.5 : OCP5 (lower) : 00001CH ch.6 : OCP6 (lower) : 000034H ch.7 : OCP7 (lower) : 00006CH bit 7 C07 R/W bit 6 C06 R/W bit 5 C05 R/W bit 4 C04 R/W bit 3 C03 R/W bit 2 C02 R/W bit 1 C01 R/W bit 0 C00 R/W Initial value XXXXXXXX B R/W : Readable and writable X : Indeterminate -- : Undefined bits (read value undefined) 50 MB90520 Series * Block diagram * Output compare 0 (OCU) #36* #35* OCU control status register ch. 23 (OCS23) -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 2 2 16-bit free-run timer 1 -- -- CST1 CST0 Output compare interrupt request Compare control circuit 3 OCP3 OCU compare register ch. 3 Compare control circuit 2 Internal data bus OCP2 OCU compare register ch. 2 Output control circuit 2 Output control circuit 3 P35/OUT3 Pin P34/OUT2 Pin P33/OUT1 Pin P32/OUT0 Pin Compare control circuit 1 OCP1 OCU compare register ch.1 Output control circuit 1 Compare control circuit 0 OCP0 OCU compare register ch. 0 2 2 Output control circuit 0 -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 -- -- CST1 CST0 #34* #33* OCU control status register ch. 01 (OCS01) Output compare interrupt request * : Interrupt number 51 MB90520 Series * Output compare 1(OCU) #27* OCU control status register ch. 67 (OCS67) -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 Output compare interrupt request -- -- CST1 CST0 2 2 16-bit free-run timer 2 Compare control circuit 7 OCP7 OCU compare register ch. 7 Internal data bus Compare control circuit 6 OCP6 OCU compare register ch. 6 Output control circuit 6 Output control circuit 7 P73/TO1/OUT7 Pin P72/TI1/OUT6 Pin P71/TO0/OUT5 Compare control circuit 5 OCP5 OCU compare register ch. 5 P70/TI0/OUT4 Compare control circuit 4 OCP4 OCU compare register ch. 4 2 2 Output control circuit 4 Output control circuit 5 Pin Pin -- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 -- -- CST1 CST0 OCU control status register ch. 45 (OCS45) #25* * : Interrupt number Output compare interrupt request 52 MB90520 Series 7. 8/16-bit Up/Down Counter/Timer 0, 1 The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit re-load compare registers, and their controllers. (1) Register Configuration * Up/down count register 0 (UDCR0) Address 000080H bit 7 D07 R Address 000081H bit 15 D17 R Address 000082H bit 7 D07 W Address 000083H bit 15 D17 W Address CSR0 : 000084H CSR1 : 000088H bit 7 CSTR R/W Address CCRL0 : 000086H CCRL1 : 00008AH bit 7 bit 6 D06 R bit 14 D16 R bit 6 D06 W bit 14 D16 W bit 6 CITE R/W bit 6 bit 5 D05 R bit 13 D15 R bit 5 D05 W bit 13 D15 W bit 5 UDIE R/W bit 5 bit 4 D04 R bit 12 D14 R bit 4 D04 W bit 12 D14 W bit 4 CMPF R/W bit 4 bit 3 D03 R bit 11 D13 R bit 3 D03 W bit 11 D13 W bit 3 bit 2 D02 R bit 10 D12 R bit 2 D02 W bit 10 D12 W bit 2 bit 1 D01 R bit 9 D11 R bit 1 D01 W bit 9 D11 W bit 1 bit 0 D00 R bit 8 D10 R bit 0 D00 W bit 8 D10 W bit 0 UDF0 R bit 0 Initial value X0 0 0 0 0 0 0 B Initial value 00000000 B Initial value 00000000 B Initial value 00000000 B Initial value 00000000 B Initial value 00000000 B * Up/down count register 1 (UDCR1) * Re-load compare register 0 (RCR0) * Re-load compare register 1 (RCR1) * Counter status register 0, 1 (CSR0, CSR1) OVFF UDFF UDF1 R/W bit 3 R/W bit 2 R bit 1 * Counter control register 0, 1 (CCRL0, CCRL1) -- CTUT R/W -- * Counter control register 0 (CCRH0) Address 000087H bit 15 bit 14 M16E CDCF R/W Address 00008BH bit 15 R/W bit 14 CDCF R/W UCRE RLDE UDCC CGSC CGE1 CGE0 R/W bit 13 CFIE R/W bit 13 CFIE R/W R/W bit 12 R/W bit 11 R/W bit 10 R/W bit 9 R/W bit 8 Initial value 00000000 B CLKS CMS1 CMS0 CES1 CES0 R/W bit 12 R/W bit 11 R/W bit 10 R/W bit 9 R/W bit 8 * Counter control register 1 (CCRH1) Initial value X0 0 0 0 0 0 0 B -- -- CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W : Readable and writable R : Read only W : Write only -- : Undefined bits (read value undefined) 53 MB90520 Series (2) Block Diagram * Block diagram of 8/16-bit up/down counter/timer 0 Internal data bus RCR0 Re-load compare register 0 Re-load control circuit UDCR0 Up/down count register 0 Counter control register 0 (CCRL0) CARRY/ BORROW (to channel 1) -- CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 Underflow Overflow P26/ZIN0/INT7 Pin Edge/level detection circuit Counter clear circuit Compare control circuit P24/AIN0 Pin Pin P25/BIN0 Prescaler Count clock Counter status register 0 (CSR0) UP/down count clock selector CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 Interrupt request #21* Interrupt request #22* M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Counter control register 0 (CCRH0) M16E (to channel 1) * : Interrupt number : Machine clock frequency 54 MB90520 Series * Block diagram of 8/16-bit up/down counter/timer 1 Internal data bus RCR1 Re-load compare register 1 Re-load control circuit Up/down count register 1 Counter control register 1 (CCRL1) UDCR1 -- CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 Underflow Overflow P52/SCK2/ZIN1 Edge/level Pin detection circuit CARRY/BORRW (from channel 0) Counter clear circuit Compare control circuit P50/SIN2/AIN1 Pin Pin P51/SOT2/BIN1 M16E (from channel 1) Prescaler Count clock Counter status (CSR1) register 1 UP/down count clock selector CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 Interrupt request #29* Interrupt request #30* -- CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Counter control register 1 (CCRH1) * : Interrupt number : Machine clock frequency 55 MB90520 Series 8. Extended I/O Serial Interface 0, 1 The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel configuration. For data transfer, you can select LSB first/MSB first. (1) Register Configuration * Serial mode control upper status register 0, 1 (SMCSH0, SMCSH1) Address SMCSH0 : 000025H SMCSH1 : 000029H bit 15 bit 14 bit 13 bit 12 SIE R/W bit 4 bit 11 SIR R/W bit 3 MODE R/W bit 3 D3 R/W bit 10 bit 9 bit 8 Initial value 00000010 B SMD2 SMD1 SMD0 R/W Address SMCSL0 : 000024H SMCSL1 : 000028H bit 7 R/W bit 6 R/W bit 5 BUSY STOP STRT R bit 2 BDS R/W bit 2 D2 R/W R/W bit 1 SOE R/W bit 1 D1 R/W R/W bit 0 SCOE R/W bit 0 D0 R/W Initial value XXXXXXXX B Initial value XXXX0 0 0 0 B * Serial mode control lower status register 0, 1 (SMCSL0, SMCSL1) -- -- -- -- -- bit 4 D4 R/W -- -- -- * Serial data register 0, 1 (SDR0, SDR1) Address SDR0 : 000026H SDR1 : 00002AH bit 7 D7 R/W bit 6 D6 R/W bit 5 D5 R/W R/W : Readable and writable R : Read only X : Indeterminate -- : Undefined bits (read value undefined) 56 MB90520 Series (2) Block Diagram Internal data bus (MSB first) D0 to D7 D7 to D0 (LSB first) Transfer direction selection Pin P45/SIN1 Pin P50/SIN2/AIN1 Pin P46/SOT1 Pin Pin P47/SCK1 Pin P52/SCK2/ZIN1 Internal clock Control circuit P51/SOT2/BIN1 Shift clock counter Serial data register (SDR) Read Write 3 0 SIR BUSY STOP STRT 2 1 SMD2 SMD1 SMD0 SIE -- -- -- -- MODE BDS SOE SCOE Serial mode control status register (SMCSH,L) *: Interrupt number Interrupt request #15 (SMCS0)* #17 (SMCS1)* 57 MB90520 Series 9. UART (SCI) UART (SCI) is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization system). * Data buffer: Full-duplex double buffer * Transfer mode:Clock synchronized (with start and stop bit) Clock asynchronized (start-stop synchronization system) * Baud rate:Embedded dedicated baud rate generator External clock input possible Internal clock (a clock supplied from 16-bit re-load timer 0 can be used.) Internal machine clock Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps For 6 MHz, 8 MHz, 10 MHz, CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps 12 MHz and 16 MHz * Data length:8 bit (without a parity bit) 7 bit (with a parity bit) * Signal format: NRZ (Non Return to Zero) system * Reception error detection: Framing error Overrun error Parity error (multi-processor mode is supported, enabling setup of any baud rate by an external clock.) * Interrupt request: Receive interrupt (reception complete, receive error detection) Transmit interrupt (transmisson complete) Transmit/receive conforms to extended intelligent I/O service (EI2OS) } 58 MB90520 Series (1) Register Configuration * Serial control register (SCR) Address 000021H bit 15 PEN R/W bit 14 P R/W bit 6 MD0 R/W bit 14 ORE R bit 13 SBL R/W bit 5 CS2 R/W bit 13 FRE R bit 12 CL R/W bit 4 CS1 R/W bit 12 bit 11 A/D R/W bit 3 CS0 R/W bit 11 bit 10 REC W bit 2 bit 9 RXE R/W bit 1 bit 8 TXE R/W bit 0 SOE R/W bit 8 TIE R/W Initial value 0 0 0 0 1X0 0 B Initial value 00000000 B Initial value 00000100 B * Serial mode register (SMR) Address 000020H bit 7 MD1 R/W Reserved SCKE R/W bit 10 -- -- R/W bit 9 RIE R/W * Serial status register (SSR) Address 000023H bit 15 PE R RDRF TRDE R R * Serial input data register (SIDR) Address 000022H bit 7 D7 R bit 6 D6 R bit 5 D5 R bit 4 D4 R bit 3 D3 R bit 2 D2 R bit 1 D1 R bit 0 D0 R Initial value XXXXXXXX B * Serial output data register (SODR) Address 000022H bit 7 D7 W bit 15 MD R/W bit 6 D6 W bit 14 -- -- bit 5 D5 W bit 13 -- -- bit 4 D4 W bit 12 -- -- bit 3 D3 W bit 11 DIV3 R/W bit 2 D2 W bit 10 DIV2 R/W bit 1 D1 W bit 9 DIV1 R/W bit 0 D0 W bit 8 DIV0 R/W Initial value 0XXX1 1 1 1 B Initial value XXXXXXXX B * Communications prescaler control register (CDCR) Address 000027H R/W:Readable and writable R : Read only W : Write only X : Indeterminate -- : Undefined bits (read value undefined) 59 MB90520 Series (2) Block Diagram Control bus Receive interrupt signal #37* Transmit interrupt signal #39* Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter Pin P43/SOT0 Dedicated baud rate generator 16-bit re-load timer 0 External clock Pin P42/SCK0 Start bit detection circuit Receive bit counter Receive parity counter Clock selector Transmit clock Receive clock Receive control circuit Pin P42/SIN0 Shift register for reception Shift register for transmission SIDR Receive condition decision circuit Reception complete SODR Start transmission To EI2OS reception error generation signal (to CPU) Internal data bus SMR register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR register PEN P SBL CL A/D REC RXE TXE SSR register PE ORE FRE RDRF TDRE RIE TIE * : Interrupt number 60 MB90520 Series 10. DTP/External Interrupt Circuit The DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit* for transmission to the F2MC-16LX CPU. It is used to activate the intelligent I/O service or interrupt processing. As with request levels, two types of "H" and "L" can be selected for the intelligent I/O service. Rising and falling edges as well as "H" and "L" can be selected for an external interrupt request. * : The external peripheral circuit is connected outside the MB90520 series device. (1) Register Configuration * DTP/interrupt factor register (EIRR) Address 000031H bit 15 ER7 R/W bit 14 ER6 R/W bit 13 ER5 R/W bit 12 ER4 R/W bit 11 ER3 R/W bit 10 ER2 R/W bit 9 ER1 R/W bit 8 ER0 R/W Initial value XXXXXXXX B * DTP/interrupt enable register (ENIR) Address 000030H bit 7 EN7 R/W bit 6 EN6 R/W bit 5 EN5 R/W bit 4 EN4 R/W bit 3 EN3 R/W bit 2 EN2 R/W bit 1 EN1 R/W bit 0 EN0 R/W Initial value 00000000 B * Request level setting register (ELVR) Address ELVR (lower) : 000032H bit 7 LB3 R/W bit 15 Address ELVR (upper) : 000033H LB7 R/W R/W: Readable and writable X : Indeterminate LA7 R/W LB6 R/W LA6 R/W LB5 R/W LA5 R/W LB4 R/W LA4 R/W bit 6 LA3 R/W bit 14 bit 5 LB2 R/W bit 13 bit 4 LA2 R/W bit 12 bit 3 LB1 R/W bit 11 bit 2 LA1 R/W bit 10 bit 1 LB0 R/W bit 9 bit 0 LA0 R/W bit 8 Initial value 00000000 B Initial value 00000000 B 61 62 Request level setting register (ELVR) LB7 2 2 2 2 2 2 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Pin Level edge selector 7 Level edge selector 5 Level edge selector 3 2 Level edge selector 1 2 (2) Block Diagram MB90520 Series P26/ZIN0/INT7 Pin Level edge selector 6 Level edge selector 4 Level edge selector 2 Level edge selector 0 P06/INT6 Pin P05/INT5 DTP/external interrupt input detection circuit *: Interrupt number Internal data bus ER7 ER6 ER5 ER4 ER3 ER2 ER1 #20* #18* #13* EN7 EN6 EN5 EN4 EN3 EN2 EN1 P04/INT4 ER0 DTP/interrupt factor register (EIRR) Interrupt request signal #24* Pin P03/INT3 Pin P02/INT2 Pin P01/INT1 Pin P00/INT0 EN0 DTP/interrupt enable register (ENIR) MB90520 Series 11. Wake-up Interrupt Wake-up interrupts transmit interrupt request ("L" level) generated by peripheral equipment located between external peripheral devices and the F2MC-16LX CPU to the CPU and invoke interrupt processing. The interrupt does not conform to the exterded intelligent I/O service (EI2OS). (1) Register Configuration * Wake-up interrupt flag register (EIFR) Address 00000FH bit 15 -- -- Address 00001FH bit 15 EN7 W bit 14 -- -- bit 14 EN6 W bit 13 -- -- bit 13 EN5 W bit 12 -- -- bit 12 EN4 W bit 11 -- -- bit 11 EN3 W bit 10 -- -- bit 10 EN2 W bit 9 -- -- bit 9 EN1 W bit 8 WIF R/W bit 8 EN0 W Initial value 00000000 B Initial value XXXXXXX0 B * Wake-up interrupt enable register (EICR) R/W: Readable and writable W : Write only -- : Undefined bits (read value undefined) (2) Block Diagram Internal data bus Wake-up interrupt enable register (EICR) EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 Wake-up interrupt flag register (EIFR) -- -- -- -- -- -- -- WIF Interrupt request detection circuit P10/WI0 Pin P11/WI1 Pin Wake-up interrupt request #16* P12/WI2 Pin P13/WI3 Pin P14/WI4 P15/WI5 P16/WI6 P17/WI7 Pin Pin Pin Pin *: Interrupt number 63 MB90520 Series 12. Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks. By using this module, hardware interrupt requests to the CPU can be generated and cancelled using software. This module does not conform to the extended intelligent I/O service (EI2OS). (1) Register Configuration * Delayed interrupt factor generation/cancellation register (DIRR) Address 00009FH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 R0 R/W Initial value XXXXXXX0 B Note: Upon a reset, an interrupt is cancelled. R/W: Readable and writable -- : Undefined bits (read value undefined) The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this register with "1" generates a delay interrupt request. Programming this register with "0" cancels a delay interrupt request. Upon a reset, an interrupt is canceled. The undefined bit area can be programmed with either "0" or "1." For future extension, however, it is recommended that bit set and clear instructions be used to access this register. (2) Block Diagram Internal data bus -- -- -- -- -- -- -- R0 S factor R latch Delayed interrupt factor generation/ cancellation register (DIRR) *: Interrupt number Interrupt request signal #42* 64 MB90520 Series 13. 8/10-bit A/D Converter The 8/10-bit A/D converter converts analog voltage input to the analog input pins (input voltage) to digital values (A/D conversion) and has the following features: * Minimum conversion time: minimum 15.0 s (at machine clock frequency of 16 MHz, including sampling time) * Minimum sampling period: 4 s/8 s (at machine clock frequency of 16 MHz) * Compare time: 99/176 machine cycles per channel (99 machine cycles are used for a machine clock frequency below 10 MHz.) * Conversion method: RC successive approximation method with a sample and hold circuit * 8/10-bit resolution * Analog input pins: Selectable from eight channels by software Single conversion mode: Selects and converts one channel. Scan conversion mode: Converts two or more successive channels. Up to eight channels can be programmed. Continuous conversion mode: Repeatedly converts specified channels. Stop conversion mode: Stops conversion after completing a conversion for one channel and wait for the next activation (conversion can be started synchronously). * Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling efficient continuous processing. * When interrupts are enabled, there is no loss of data even in continuous operations because the conversion data protection function is in effect. * Starting factors for conversion: Selectable from software activation, external trigger (falling edge) and timer (rising edge). 65 MB90520 Series (1) Register Configuration * A/D control status register upper digits (ADCS2) Address 000037H bit 15 BUSY R/W bit 14 INT R/W bit 13 INTE R/W bit 12 PAUS R/W bit 11 STS1 R/W bit 10 STS0 R/W bit 9 bit 8 STRT Reserved W R/W Initial value 00000000 B * A/D control status register lower digits (ADCS1) Address 000036H bit 7 MD1 R/W bit 6 MD0 R/W bit 5 ANS2 R/W bit 4 ANS1 R/W bit 3 ANS0 R/W bit 2 ANE2 R/W bit 1 ANE1 R/W bit 0 ANE0 R/W Initial value 00000000 B * A/D data register upper digits (ADCR2) Address 000039H bit 15 SELB W bit 14 ST1 W bit 13 ST0 W bit 12 CT1 W bit 11 CT0 W bit 10 -- -- bit 9 (D9) R bit 8 (D8) R Initial value 0 0 0 0 1XXX B * A/D data register lower digits (ADCR1) Address 000038H bit 7 D7 R R/W: R: W: X: --: bit 6 D6 R bit 5 D5 R bit 4 D4 R bit 3 D3 R bit 2 D2 R bit 1 D1 R bit 0 D0 R Initial value XXXXXXXX B Readable and writable Read only Write only Indeterminate Undefined bits (read value undefined) 66 MB90520 Series (2) Block Diagram A/D control status register (ADCS) Interrupt request #11* BUSY INT INTE PAUS STS1 STS0 STRT Reserved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 6 P27/ADTG P73/TO1/OUT7 2 Clock selector Decoder Comparator P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 Sample hold circuit Analog channel selector AVRH, AVRL AVCC AVSS 8-bit D/A converter Control circuit A/D data register SELB ST1 ST0 CT1 CT0 (ADCR) -- (D9) (D8) D7 D6 D5 D4 D3 D2 D1 D0 TO : 16-bit re-load timer channel 1 output * : Interrupt number : Machine clock frequency Internal data bus 67 MB90520 Series 14. 8-bit D/A Converter The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two channels, each of which can be controlled in terms of output by the D/A control register. (1) Register Configuration * D/A converter data register ch.0 (DADR0) Address 00003AH bit 7 DA07 R/W bit 6 DA06 R/W bit 5 DA05 R/W bit 4 DA04 R/W bit 3 DA03 R/W bit 2 DA02 R/W bit 1 DA01 R/W bit 0 DA00 R/W Initial value XXXXXXXX B * D/A converter data register ch.1 (DADR1) Address 00003BH bit 15 DA17 R/W bit 14 DA16 R/W bit 13 DA15 R/W bit 12 DA14 R/W bit 11 DA13 R/W bit 10 DA12 R/W bit 9 DA11 R/W bit 8 DA10 R/W Initial value XXXXXXXX B * D/A control register 0 (DACR0) Address 00003CH bit 7 -- -- bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 -- -- bit 2 -- -- bit 1 -- -- bit 0 DAE0 R/W Initial value XXXXXXX0 B * D/A control register 1 (DACR1) Address 00003DH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 DAE1 R/W Initial value XXXXXXX0 B R/W: Readable and writable X : Indeterminate -- : Undefined bits (read value undefined) 68 MB90520 Series * Block Diagram Internal data bus D/A converter data register ch.1 (DADR1) DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 D/A converter data register ch.0 (DADR0) DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 D/A converter 1 DVRH DA17 Pin 2R DA16 2R DA15 2R DA14 2R DA13 2R DA12 2R DA11 2R DA10 2R 2R DVSS Standby control R P54/DA1 D/A converter 0 DVRL DA07 Pin 2R DA06 2R DA05 2R DA04 2R DA03 2R DA02 2R DA01 2R DA00 2R R P53/DA0 R R R R R R R R R R R R 2R DVSS Standby control D/A control register 1 (DACR1) -- -- -- -- -- -- -- DAE1 D/A control register 0 (DACR0) -- -- -- -- -- -- -- DAE0 Internal data bus 69 MB90520 Series 15. Clock Timer The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt. (1) Register Configuration * Clock timer control register (WTC) Address 0000AAH bit 7 WDCS R/W R/W: Readable and writable R : Read only X : Indeterminate bit 6 SCE R bit 5 bit 4 bit 3 WTR R/W bit 2 bit 1 bit 0 Initial value 1X0 0 1 0 0 0 B WTIE WTOF R/W R/W WTC2 WTC1 WTC0 R/W R/W R/W (2) Block Diagram To watchdog timer Timer counter LCLK x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 OF OF OF OF OF OF OF Power-on reset Shift to a hardware stand-by Shift to stop mode Interval timer selector Counter clear circuit To sub-clock stabilization time controller Clock timer interrupt request #22* WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clock timer control register (WTC) * : Interrupt number OF : Overflow LCLK : Sub-clock frequency 70 MB90520 Series 16.LCD Controller/Driver The LCD (liquid crystal display) controller/driver, which contains a 16-byte display data memory, controls LCD indication using four common output pins and 32 segment output pins. It can select three types of duty output and directly drive the LCD panel. (1) Register Configuration * LCDC control register 0 (LCR0) Address 00006AH bit 7 CSS R/W bit 6 LCEN R/W bit 5 VSEL R/W bit 4 BK R/W bit 3 MS1 R/W bit 2 MS0 R/W bit 1 FP1 R/W bit 0 FP0 R/W Initial value 00010000 B * LCDC control register 1 (LCR1) Address 00006BH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value 00000000 B Reserved SEG5 R/W R/W SEG4 Reserved SEG3 R/W R/W R/W SEG2 SEG1 SEG0 R/W R/W R/W * Port 7/COM pin selection register (LCDCMR) Address 00000BH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 bit 10 bit 9 bit 8 COM3 COM2 COM1 COM0 R/W R/W R/W R/W Initial value XXXX0 0 0 0 B * RAM for LCD indication (VRAM) Address 000070H to 00007FH bit 7 b7 R/W bit 6 b6 R/W bit 5 b5 R/W bit 4 b4 R/W bit 3 b3 R/W bit 2 b2 R/W bit 1 b1 R/W bit 0 b0 R/W Initial value XXXXXXXX B R/W: Readable and writable X : Indeterminate -- : Undefined bits (read value undefined) 71 MB90520 Series (2) Block Diagram Pin LCDC control register 0 (LCR0) CSS LCEN VSEL BK MS1 MS0 FP1 FP0 Pin Split resistor Pin Pin 2 Pin HCLK LCLK Prescaler Timing controller generator V0 V1 V2 V3 P74/COM0 P75/COM1 P76/COM2 P77/COM3 SEG00 SEG01 SEG02 Common driver Internal data bus Pin Pin Pin AC Pin Indication RAM (16 bytes) 32 Pin 6 Segment driver Pin ......... Pin Pin Pin Reserved SEG5 SEG4 Reserved SEG3 SEG2 SEG1 SEG0 LCDC control register 1 (LCR1) Controller section P95/SEG29 P96/SEG30 P97/SEG31 HCLK : Oscillation frequency LCLK : Sub-clock frequency 72 ......... MB90520 Series 17. Communications Prescaler Register This register controls machine clock division. Output from the communications prescaler register is used for UART (SCI) and extended I/O serial interface. The communications prescaler register is so designed that a constant baud rate may be acquired for various machine clocks. (1) Register Configuration * Communications prescaler control register (CDCR) Address 000027H bit 15 MD R/W bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 DIV3 R/W bit 10 DIV2 R/W bit 9 DIV1 R/W bit 8 DIV0 R/W Initial value 0XXX1 1 1 1 B R/W: Readable and writable -- : Undefined bits (read value undefined) 73 MB90520 Series 18. Address Match Detection Function When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at "1," the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. (1) Register Configuration * Program address detection register 0 to 2 (PADR0) Address PADR0 (High order address) : 001FF2H R/W Address PADR0 (Middle order address) : 001FF1H R/W Address PADR0 (Low order address) : 001FF0H R/W Address PADR1 (High order address) : 001FF5H R/W Address PADR1 (Middle order address) : 001FF4H R/W Address PADR1 (Low order address) : 001FF3H R/W Address bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value 00000000 B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 15 R/W bit 14 R/W bit 13 R/W bit 12 R/W bit 11 R/W bit 10 R/W bit 9 R/W bit 8 Initial value XXXXXXXX B bit 23 R/W bit 22 R/W bit 21 R/W bit 20 R/W bit 19 R/W bit 18 R/W bit 17 R/W bit 16 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 15 R/W bit 14 R/W bit 13 R/W bit 12 R/W bit 11 R/W bit 10 R/W bit 9 R/W bit 8 Initial value XXXXXXXX B bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 Initial value XXXXXXXX B * Program address detection register 3 to 5 (PADR1) * Program address detection control status register (PACSR) 00009EH Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W: Readable and writable X : Indeterminate -- : Undefined bits (read value undefined) 74 MB90520 Series (2) Block Diagram Compare Address latch Internal data bus Address detection register INT9 instruction Enable bit F2MC-16LX CPU core 75 MB90520 Series 19. ROM Mirroring Function Selection Module The ROM mirror function select module enables the ROM data from the FF bank to be read also from the 00 bank. (1) Register Configuration * ROM mirroring function selection register (ROMM) Address 00006FH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 MI W Initial value XXXXXXX1 B W : Write only -- : Undefined bits (read value undefined) Note: Do not access this register during operation at addresses 004000H to 00FFFFH. (2) Block Diagram ROM mirroring function selection register (ROMM) Internal data bus Address area Address FF bank 00 bank Data ROM 76 MB90520 Series 20. Low-power Consumption (Stand-by) Mode The F2MC-16LX has the following CPU operating modes configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode : A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation clock. Main clock mode: A mode in which the CPU and peripheral equipment are driven by drivided-by-2 of the oscillation clock. The PLL multiplication circuits stops in the main clock mode. * Sub-clock mode The sub-clock mode causes the CPU to operate only with the sub-clock. This mode uses the sub-clock frequency divided by four as the operating clock frequency while stopping the main clock and PLL clock. * CPU intermittent operation mode The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU intermittently while external bus and peripheral functions are operated at a high speed. * Hardware stand-by mode The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU by the low-power consumption control circuit (sleep mode), stopping clock supplies to the CPU and peripheral functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware stand-by mode). Of these modes, modes other than the PLL clock mode are low power consumption modes. (1) Register Configuration * Clock select register (CKSCR) Address 0000A1H bit 15 SCM R Address 0000A0H bit 14 MCM R bit 13 WS1 R/W bit 12 WS0 R/W bit 11 SCS R/W bit 10 MCS R/W bit 9 CS1 R/W bit 8 CS0 R/W Initial value 11111100 B * Low-power consumption mode control register (LPMCR) bit 7 STP W bit 6 SLP W bit 5 SPL R/W bit 4 RST W bit 3 TMD W bit 2 CG1 R/W bit 1 CG0 R/W bit 0 SSR R/W Initial value 00011000 B R/W: Readable and writable R : Read only W : Write only 77 MB90520 Series (2) Block Diagram Standby control circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 SSR CPU intermittent operation cycle selector 2 Clock mode Sleep signal Stop signal CPU clock control circuit CPU operation clock Hardware standby Peripheral clock control circuit S R S R Q Q S R S R Q Q Machine clock Peripheral function operation clock Reset Interrupt Clock selector 2 Oscillation stabilization time selector 2 PLL multiplication circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR) X0 X1 Pin Pin Clock oscillator Oscillation clock Dividedby-2 Main clock Dividedby-2048 Dividedby-4 Dividedby-4 Dividedby-8 Timebase timer To watchdog timer X0A Pin X1A Pin Sub-clock Sub-clock oscillator Dividedby-1024 Dividedby-8 Dividedby-2 Dividedby-2 Clock timer S : Set R : Reset Q : Output 78 MB90520 Series 21.Clock Monitor Function The clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from the CKOT pin. (1) Register configuration * Clock output enable register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXX1B Address 00003EH CKEN FRQ2 R/W R/W FRQ1 FRQ0 R/W R/W R/W:Readable and writable --:Undefined bits (read value undefined) (2) Block Diagram Internal data bus CKEN FQR2 FQR1 FQR0 Divider circuit P31/CKOT : Machine clock frequency 79 MB90520 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC Power supply voltage AVRH, AVRL DVCC Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total average output current Power consumption Operating temperature Storage temperature *1: *2: *3: *4: *5: *6: VI VO IOL IOLAV IOLAV IOH IOHAV IOHAV PD TA Tstg Rating Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 -55 Max. VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 6.0 VCC + 6.0 15 4 100 50 -15 -4 -100 -50 300 +85 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mW C C *6 *6 *4 *5 *1 *1 *2 *3 *3 *4 *5 Remarks "L" level total maximum output current IOL "H" level total maximum output current IOH AVCC, AVRH, AVRL, and DVCC shall never exceed VCC. AVRL shall never exceed AVRH. VCC AVCC DVCC 3.0V VI and VO shall never exceed VCC + 0.3 V. The maximum output current is a peak value for a corresponding pin. Average output current is an average current value observed for a 100 ms period for a corresponding pin. Total average current is an average current value observed for a 100 ms period for all corresponding pins. Note: Average output current = operating current x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 80 MB90520 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol VCC Power supply voltage VCC VCC Smoothing capacitor Operating temperature CS TA Value Min. 3.0 4.0 3.0 0.1 -40 Max. 5.5 5.5 5.5 1.0 +85 Unit V V V F C Remarks Normal operation (MB90522, MB90523) Normal operation (MB90F523) Guaranteed frequency = 10 MHz at 4.0 V to 4.5V Retains status at the time operation stops * * : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. * C pin diagram C CS 81 MB90520 Series 3. DC Characteristics (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. Parameter Symbol Pin name P20 to P27, P30 to P37, P53, P54, P70 to P77, P80 to P87, PA0 to PA7, MD0 to MD2 P20 to P27, P30 to P37, P53, P54, P70 to P77, P80 to P87, PA0 to PA7, MD0 to MD2 Other than P90 to P97 All output pins "H" level input voltage VIHS 0.8 VCC VCC = 3.0 V to 5.5 V (MB90523) VCC - 0.3 VCC = 4.0 V to 5.5 V (MB90F523) -- VCC + 0.3 V VIHM -- VCC + 0.3 V "L" level input voltage VILS VSS - 0.3 -- 0.2 VCC V VILM "H" level output voltage "L" level output voltage VOH VSS - 0.3 VCC = 4.5 V, IOH = -2.0 mA VCC = 4.5 V, IOL = 2.0 mA VCC - 0.5 -- -- VSS + 0.3 -- V V VOL -- -- 0.4 V Open-drain output Ileak leakage current Input leakage current Pull-up resistance Pull-down resistance IIL Output pin P90 to P97 Other than P90 to P97 P00 to P07, P10 to P17, P40 to P47, RST, MD0, MD1 MD2 -- -- 0.1 5 A VCC = 5.5 V, VSS < VI < VCC -5 -- 5 A RUP -- 15 30 100 k RDOWN -- 15 30 100 k (Continued) 82 MB90520 Series (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. Internal operation at 16 MHz VCC at 5.0 V Normal operation Internal operation at 16 MHz VCC at 5.0 V A/D converter operation Internal operation at 16 MHz VCC at 5.0 V D/A converter operation When data is written or erased in flash mode Internal operation at 16 MHz VCC at 5.0 V In sleep mode Internal operation at 8 kHz VCC at 5.0 V TA = +25C Subsystem operation Internal operation at 8 kHz VCC at 5.0 V TA = +25C In subsleep mode Internal operation at 8 kHz VCC at 5.0 V TA = +25C In clock mode TA = +25C In stop mode -- -- -- -- -- -- -- 30 85 35 90 40 95 40 130 45 140 50 145 mA MB90522, MB90523 Parameter Symbol ICC ICC ICC ICC ICC ICC VCC VCC VCC VCC VCC VCC Pin name mA MB90F523 mA MB90522, MB90523 mA MB90F523 mA MB90522, MB90523 mA MB90F523 ICC ICCS Power supply current* ICCS ICCL VCC VCC VCC VCC -- -- -- -- 95 7 25 0.1 140 12 30 1.0 mA MB90F523 mA MB90522, MB90523 mA MB90F523 mA MB90522, MB90523 ICCL VCC -- 4 7 mA MB90F523 A MB90522, MB90523 ICCLS ICCLS ICCT ICCT ICCH ICCH Input CIN capacitance VCC VCC VCC VCC VCC VCC Other than AVCC, AVSS, C, VCC, VSS -- -- -- -- -- -- -- 30 0.1 15 30 5 0.1 10 50 1 30 50 20 10 80 mA MB90F523 A A A A pF MB90522, MB90523 MB90F523 MB90522, MB90523 MB90F523 (Continued) 83 MB90520 Series (Continued) Parameter Symbol LCD split resistor Pin name V0 to V1, V1 to V2, V2 to V3 COM0 to COM3 V1 to V3 = 5.0 V SEG00 to SEG31 (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. -- 50 100 200 k RLCD Output impedance RVCOM for COM0 to COM3 Output impedance RVSEG for SEG00 to SEG31 LCDC leak ILCDC current -- -- 2.5 k -- -- 15 k V0 to V3, COM1 to COM3, SEG00 to SEG31 -- -- -- 5 A * : The current value is preliminary and may be subject to change for enhanced characteristics without previous notice.The power supply current is measured with an external clock. 84 MB90520 Series 4. AC Characteristics (1) Reset, Hardware Standby Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tRSTL tHSTL RST HST -- 4 tCP* 4 tCP* -- -- ns ns Parameter Reset input time Hardware standby input time * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC * Measurement conditions for AC ratings Pin CL CL is a load capacitance connected to a pin under test. CL of 80 pF must be connected to address data bus (AD15 to AD00). 85 MB90520 Series (2) Specification for Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Max. 0.05 30 ms * Due to repeated 4 -- ms operations Parameter Power supply rising time Power supply cut-off time Symbol Pin name Condition tR tOFF VCC VCC -- * : VCC must be kept lower than 0.2 V before power-on. Notes: * The above ratings are values for causing a power-on reset. * There are internal registers which can be initialized only by a power-on reset. Apply power according to this rating to ensure initialization of the registers. tR VCC 2.7 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage when the PLL clock is not in use. If the voltage drops 1 V or less per second, however, the PLL clock may be used. VCC 0.2 V 0.2 V VSS It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. 86 MB90520 Series (3) Clock Timings (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Parameter Min. Typ. Max. FC X0, X1 -- 3 -- 16 MHz 4.0 V to Clock frequency FC X0, X1 3 -- 10 MHz MB90F523 4.5 V FCL X0A, X1A -- 32.768 -- kHz -- tHCYL X0, X1 62.5 -- 333 ns 4.0 V to X0, X1 Clock cycle time tHCYL 100 -- 333 ns MB90F523 4.5 V X0A, X1A -- -- 30.5 -- s tLCYL Recommended PWH, X0 -- 10 -- -- ns duty ratio of PWL 30% to 70% Input clock pulse width PWLH, X0A -- -- 15.2 -- s PWLL tCR, External clock Input clock rising/falling time X0, X0A -- -- -- 5 ns tCF operation When the main -- -- 1.5 -- 16 MHz fCP clock is used 4.0 V to When the main fCP -- Internal operating clock 1.5 -- 10 MHz 4.5 V clock is used frequency When the -- -- -- 8.192 -- kHz subclock is fLCP used When the main -- -- 62.5 -- 333 ns tCP clock is used 4.0 V to When the main -- 100 -- 333 ns Internal operating clock cycle tCP 4.5 V clock is used time When the -- -- -- 122.1 -- s subclock is tLCP used Frequency fluctuation rate f -- -- -- -- 5 %* locked * : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. + + f = | | x 100 (%) fO Center frequency fO - - The PLL frequency deviation changes periodically from the preset frequency "(about CLK x (1CYC to 50 CYC)," thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with long intervals). 87 MB90520 Series * X0, X1 clock timing tHCYL 0.8 VCC X0 PWH tCF 0.8 VCC 0.2 VCC PWL tCR 0.2 VCC 0.8 VCC * X0A, X1A clock timing tLCYL 0.8 VCC X0A PWLH tCF 0.8 VCC 0.2 VCC PWLL tCR 0.2 VCC 0.8 VCC * PLL operation guarantee range (V) Power supply voltage VCC Relationship between internal operating clock frequency and power supply voltage MB90F523 operation guarantee range 5.5 4.5 4.0 3.3 3.0 MB90522,MB90523 operation guarantee range PLL operation guarantee range MB90V520 operation guarantee range 1 3 10 8 Internal clock fCP 12 16 (MHz) Relationship between oscillating frequency and internal operating clock frequency (MHz) 16 Internal clock fCP 12 8 4 3 2 1 2 3 4 6 8 Oscillation clock FC 12 16 (MHz) Multiplied Multiplied Multiplied -by-3 -by-2 -by-4 Multiplied -by-1 Not multiplied 88 MB90520 Series The AC ratings are measured for the following measurement reference voltages. * Input signal waveform Hystheresis input pin 0.8 VCC 0.2 VCC Pins other than hystheresis input/MD input 0.7 VCC 0.3 VCC * Output signal waveform Hystheresis input pin 2.4 VCC 0.8 VCC 89 MB90520 Series (4) Recommended Resonator Manufacturers * Sample application of ceramic resonator X0 R * X1 XTAL C1 C2 * Mask ROM product (MB90522, MB90523) Resonator manufacturer Resonator CSA2.00MG040 CSA4.00MG040 Murata Mfg. Co., Ltd. CSA8.00MTZ CSA16.00MXZ040 CSA32.00MXZ040 CCR3.52MC3 to CCR6.96MC3 TDK Corporation CCR7.0MC5 to CCR12.0MC5 CCR20.0MSC6 to CCR32.0MSC6 Frequency (MHz) 2.00 4.00 8.00 16.00 32.00 3.52 to 6.96 7.00 to 12.00 20.00 to 32.00 C1 (pF) 100 100 30 15 5 Built-in C2 (pF) 100 100 30 15 5 Built-in R Not required Not required Not required Not required Not required Not required Built-in Built-in Not required Built-in Built-in Not required (Continued) 90 MB90520 Series (Continued) * Flash ROM product (MB90F523) Resonator Resonator manufacturer CSA2.00MG040 CSA4.00MG040 Murata CSA8.00MTZ Mfg. Co., Ltd. CSA16.00MXZ040 CSA32.00MXZ040 CCR3.52MC3 to CCR6.96MC3 TDK Corporation CCR7.0MC5 to CCR12.0MC5 CCR20.0MSC6 to CCR32.0MSC6 Frequency (MHz) 2.00 4.00 8.00 16.00 32.00 3.52 to 6.96 7.0 to 12.0 20.0 to 32.0 C1 (pF) 100 100 30 15 5 Built-in C2 (pF) 100 100 30 15 5 Built-in R Not required Not required Not required Not required Not required Not required Built-in Built-in Not required Built-in Built-in Not required Inquiry:Murata Mfg. Co., Ltd.. * Murata Electronics North America, Inc.: TEL 1-404-436-1300 * Murata Europe Management GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.): TEL 65-758-4233 TDK Corporation * TDK Corporation of America Chicago Regional Office: TEL 1-708-803-6100 * TDK Electronics Europe GmbH Components Division: TEL 49-2102-9450 * TDK Singapore (PTE) Ltd.: TEL 65-273-5022 * TDK Hong Kong Co., Ltd.: TEL 852-736-2238 * Korea Branch, TDK Corporation: TEL 82-2-554-6636 91 MB90520 Series (5) UART (SCI) Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tSCYC 8 tCP* SCK0 to SCK2 -- ns SCK0 to SCK2, Internal shift clock tSLOV - 80 80 ns SOT0 to SOT2 mode SCK0 to SCK2, CL = 80 pF 100 -- ns tIVSH + 1 TTL for an SIN0 to SIN2 SCK0 to SCK2, output pin tSHIX 60 -- ns SIN0 to SIN2 tSHSL tSLSH tSLOV tIVSH tSHIX SCK0 to SCK2 SCK0 to SCK2 External shift clock mode SCK0 to SCK2 CL = 80 pF SOT0 to SOT2 + 1 TTL for an SCK0 to SCK2, output pin SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 4 tCP* 4 tCP* -- 60 60 -- -- 150 -- -- ns ns ns ns ns Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Notes: * These are AC ratings in the CLK synchronous mode. * CL is the load capacitor value connected to pins while testing. 92 MB90520 Series * Internal shift clock mode SCK 0.8 V tSLOV SOT 2.4 V 0.2 V tSCYC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SIN * External shift clock mode SCK 0.2 VCC tSLOV SOT tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SIN 93 MB90520 Series (6) Timer Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. IC00,IC01,IC10, tTIWH, -- 4 tCP* -- ns tTIWL IC11,TI0, TI1 Parameter Input pulse width * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 0.8 VCC IN tTIWH 0.8 VCC 0.2 VCC 0.2 VCC tTIWL (7) Timer Output Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. OUT0 to OUT3, PG00, -- 30 -- ns tTO PG01,PG10, PG11 Parameter CLK TOUT transition time 2.4 V CLK tTO TOUT 2.4 V 0.8 V 94 MB90520 Series 5. A/D Converter (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, 3.0 V AVRH - AVRL, TA = -40C to +85C) Value Symbol Pin name Condition Unit Min. Typ. Max. -- -- -- 8/10 -- bit -- -- -- -- 5.0 LSB -- -- -- -- 2.5 LSB -- VOT VFST -- -- IAIN VAIN -- -- IA Power supply current IAH IR Reference voltage supply current Offset between channels IRH -- -- AN0 to AN7 AN0 to AN7 -- -- AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN7 Supply current when CPU stopped and 8/10-bit A/D converter not in operation (VCC = AVCC = AVRH = 5.0 V) -- Supply current when CPU stopped and 8/10-bit A/D converter not in operation (VCC = AVCC = AVRH = 5.0 V) -- -- VCC = 5.0 V 10% at machine clock of 16 MHz VCC = 5.0 V 10% at machine clock of 16 MHz -- -- 1.9 LSB mV mV ns ns A V V V mA A A A Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog port input current Analog input voltage Reference voltage AVSS AVSS +0.5 LSB -3.5 LSB +4.5 LSB AVRH -6.5LSB 240 tCP* 64 tCP* -- AVRL AVRL + 2.7 0 -- -- -- -- AVRH AVRH -1.5 LSB +1.5 LSB -- -- -- -- -- -- 5 -- 400 -- -- -- 10 AVRH AVCC AVRH -2.7 -- 5 -- 5 -- -- -- 4 LSB * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." 95 MB90520 Series 6. A/D Converter Glossary Resolution: Analog changes that are identifiable with the A/D converter Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error, full-scale transition error and linearity error. Total error 3FF 3FE 3FD Actual conversion characteristics 0.5 LSB {1 LSB x (N - 1) + 0.5 LSB} Digital output 004 003 002 001 VNT (measured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB AVRL Analog input AVRH VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB 1 LSB = (Theoretical value) AVRH - AVRL 1024 [V] Total error for digital output N = [LSB] VOT (Theoretical value) = AVRL + 0.5 LSB [V] VFST (Theoretical value) = AVRH - 1.5 LSB [V] VNT: Voltage at a transition of digital output from (N - 1) to N (Continued) 96 MB90520 Series (Continued) Linearity error 3FF 3FE 3FD Actual conversion characteristics {1 LSB x (N - 1) + VOT} N+1 VFST (measured value) Actual conversion characteristics Differential linearity error Theoretical characteristics N Digital output Digital output 004 003 002 001 Theoretical characteristics VOT (mesured value) AVRL Analog input VNT (measured value) Actual conversion characteristics N-1 V(N + 1)T (measured value) VNT (measured value) Actual conversion characteristics N-2 AVRH AVRL Analog input AVRH VNT - {1 LSB x (N - 1) + VOT} Linearity error of [LSB] digital output N = 1 LSB Differential linearity error = of digital N 1 LSB = VFST - VOT V(N + 1)T - VNT 1 LSB - 1 LSB [LSB] [V] 1022 VOT : Voltage at transition of digital output from "000H" to "001H" VFST: Voltage at transition of digital output from "3FEH" to "3FFH" 7. Notes for A/D Conversion Analog inputs should have external circuit impedance of approximately 5 k or less. External capacitance, if used, should be several thousand times the level of the chip's internal capacitance in consideration of the effects of partial potential between the external and internal capacitance. If the impedance of the external circuit is too high, the analog voltage sampling interval may be insufficient (using a sampling interval of 4.00 s and a machine clock frequency of 16 MHz). * Block diagram of analog input circuit model Analog input RON C Comparator MB90522, MB90523 RON: Approx. 1.5 k C: Approx. 30 pF MB90F523 RON: Approx. 3.0 k C: Approx. 65 pF Note: Listed values must be considered standards. * Error The smaller | AVRH - AVRL | is, the greater the error is. 97 MB90520 Series 8. D/A Converter (AVCC = VCC = 5.0 V 10%, AVSS = VSS = DVSS = 0.0 V, TA = -40C to +85C) Parameter Resolution Differential linearity error Absolute accuracy Linearity error Conversion time Analog reference voltage Reference voltage supply current Analog output impedance Symbol -- -- -- -- -- -- IDVR IDVRS -- DVCC DVCC DVCC -- Pin name -- -- -- -- -- Value Min. -- -- -- -- -- VSS + 3.0 -- -- -- Typ. 8 -- -- -- 10 -- -- -- 20 Max. -- 0.9 1.2 1.5 20 AVCC 300 10 -- Unit Remarks bit LSB % LSB s Load capacitance: 20 pF V A A In sleep mode k 98 MB90520 Series s EXAMPLE CHARACTERISTICS (1) Power Supply Current (MB90523) ICC - VCC ICC (mA) 35 TA = +25C 30 25 20 15 10 5 3.0 4.0 ICC - TA ICC (mA) 35 VCC = 5.0 V 30 25 20 15 10 5 Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz -20 +10 +40 +70 +100 TA (C) ICCL - VCC ICCL (A) 160 TA = +25C 140 120 100 80 60 40 20 3.0 4.0 5.0 6.0 VCC (V) 20 10 3.0 Fc = 8 kHz ICCLS (mA) 70 60 50 40 30 ICCS (mA) 10 9 8 7 6 5 4 3 2 1 -20 5.0 Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 6.0 VCC (V) ICCS (mA) 10 9 8 7 6 5 4 3 2 1 3.0 ICCS - VCC TA = +25C Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 4.0 ICCS - TA 5.0 6.0 VCC (V) VCC = 5.0 V Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz +10 +40 +70 +100 TA (C) ICCLS - VCC TA = +25C Fc = 8 kHz 4.0 5.0 6.0 VCC (V) 99 MB90520 Series ICC - Fc ICC (mA) 35 TA = +25C 30 25 20 15 10 5 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V ICCS (mA) 10 9 8 7 6 5 4 3 2 1 4.0 6.0 8.0 12.0 16.0 Fc (MHz) ICCH (A) 10 9 8 Fc = 8 kHz 7 6 5 4 3 2 1 3.0 4.0 ICCT - TA ICCT (A) 10 9 8 7 6 5 4 3 2 1 -20 +10 +40 +70 +100 TA (C) VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V ICCL (A) 10 9 8 7 6 5 4 3 2 1 -20 5.0 6.0 VCC (V) 3.0 4.0 ICCS - Fc TA = +25C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 6.0 8.0 ICCH - VCC 12.0 16.0 Fc (MHz) ICCT - VCC ICCT (A) 20 18 16 14 12 10 8 6 4 2 TA = +25C TA = +25C 4.0 ICCH - TA 5.0 6.0 VCC (V) VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +10 +40 +70 +100 TA (C) 100 MB90520 Series ICCL - TA ICCL (A) 20 18 16 14 12 10 8 6 4 2 -20 +10 +40 +70 +100 TA (C) ICCLS (A) 14 12 10 8 6 4 2 -20 ICCLS - TA VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +10 +40 +70 +100 TA (C) (2) Power Supply Current (MB90F523) ICC - VCC ICC (mA) 140 TA = +25C 120 100 80 60 40 20 Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 35 Fc = 16 MHz 30 25 20 15 10 5 3.0 4.0 ICC - TA ICCS (mA) 40 35 Fc = 16 MHz Fc = 12.5 MHz 60 40 20 Fc = 10 MHz Fc = 8 MHz 15 Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 10 5 -20 +10 +40 +70 +100 TA (C) -20 +10 +40 +70 30 25 20 Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz +100 TA (C) 5.0 6.0 VCC (V) 3.0 4.0 ICCS - TA 5.0 Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz Fc = 16 MHz ICCS (mA) 40 TA = +25C ICCS - VCC 6.0 VCC (V) ICC (mA) 120 100 80 VCC = 5.0 V VCC = 5.0 V 101 MB90520 Series ICCS - VCC ICCLS (A) 200 180 160 140 120 100 80 60 40 20 3.0 4.0 5.0 6.0 VCC (V) ICCS - Fc ICCS (mA) 40 TA = +25C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V 60 40 20 VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 20 15 10 5 4.0 8.0 12.0 ICCH - VCC ICCH (A) 10 TA = +25C 40 Fc = 8 kHz 30 9 8 7 6 5 20 4 3 10 2 1 3.0 4.0 5.0 6.0 VCC (V) 3.0 4.0 5.0 6.0 VCC (V) 35 30 25 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 16.0 Fc (MHz) Fc = 8 MHz TA = +25C ICC - Fc ICC (mA) 120 TA = +25C 100 80 4.0 8.0 12.0 16.0 Fc (MHz) ICCT - VCC ICCT (A) 50 TA = +25C 102 MB90520 Series ICCT - TA ICCT (A) 10 9 8 7 6 5 4 3 2 1 -20 +10 +40 +70 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +100 TA (C) ICCLS - TA ICCLS (A) 20 18 16 14 12 10 8 6 4 2 -20 +10 +40 +70 +100 TA (C) ICCH (A) 10 9 8 7 6 5 4 3 2 1 -20 ICCH - TA +10 +40 +70 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +100 TA (C) VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 103 MB90520 Series s ORDERING INFORMATION Part number MB90523PFF MB90522PFF MB90F523PFF MB90523PFV MB90522PFV MB90F523PFV Package 120-pin Plastic LQFP (FPT-120P-M05) 120-pin Plastic QFP (FPT-120P-M13) Remarks 104 MB90520 Series s PACKAGE DIMENSIONS 120-pin Plastic LQFP (FPT-120P-M05) 16.000.20(.630.008)SQ 14.000.10(.551.004)SQ 90 61 91 60 0.08(.003) Details of "A" part 1.50 -0.10 +0.20 +.008 (Mounting height) INDEX .059 -.004 120 31 "A" 0~8 LEAD No. 1 30 0.40(.016) 0.160.03 (.006.001) 0.07(.003) M 0.1450.055 (.006.002) 0.500.20 (.020.008) 0.45/0.75 (.018/.030) 0.100.10 (.004.004) (Stand off) 0.25(.010) C 1998 FUJITSU LIMITED F120006S-3C-4 Dimensions in mm (inches) 120-pin Plastic QFP (FPT-120P-M13) 90 22.600.20(.890.008)SQ 20.000.10(.787.004)SQ 3.85(.152)MAX (Mounting height) 61 0.05(.002)MIN (STAND OFF) 60 91 14.50 (.571) REF 21.60 (.850) NOM Details of "A" part 0.15(.006) 0.15(.006) INDEX 0.15(.006)MAX 0.40(.016)MAX "A" 1 30 120 31 Details of "B" part 0.1250.05 (.005.002) 0 10 LEAD No. 0.50(.0197) 0.200.10 (.008.004) 0.08(.003) M 0.500.20(.020.008) 0.10(.004) "B" C 1995 FUJITSU LIMITED F120013S-2C-3 Dimensions in mm (inches) 105 MB90520 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F0012 (c) FUJITSU LIMITED Printed in Japan |
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